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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3142a1de301sm1702185eec.24.2026.07.16.20.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 20:42:24 -0700 (PDT) Date: Thu, 16 Jul 2026 20:42:22 -0700 From: Peter Chen To: Thinh Nguyen Cc: Krishna Kurapati , Krzysztof Kozlowski , Dmitry Baryshkov , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Wesley Cheng , "linux-arm-msm@vger.kernel.org" , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v4 1/2] dt-bindings: qcom,snps-dwc3: Add property indicating presence of eUSB2 phy Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE3MDAzMSBTYWx0ZWRfXz74loxA8Z0Lz 5XkQl1YqdhY1bFd5njfKMuswY24REc/2WA8vA5Qml7r3w4TbOTzCCVnS5gKYSzumZJmaiV5b5Rm 0YjCUrDJKU0yiHD/5FJPGY27QO785Tdb6xSNG2N623Lh1iQjilmxpK2lgkf+V4SnqkchAtobTI8 secoPSsOZoxugrJQKA7VcQouwYLIntVIyAuevw2EVOkXS4VC1hHfVjqSp3MZkNUfORwdT/Cy1NK SAPqFu5TVYD/ZXsq0TePpvNEma8P4W8msIrCJoO3ueeeTdyQZgZSGfXYTNBngA0YHWHapoMp4JJ nKSZp7+RUTlSxcv+afKlyt/ItpC19g9QkiCvSYksPB7uCutY5Ukjry4SEGoNnhDSU+8Biepyb8I qUCuiP3g7Z/fqXAy+gcc9hgr7dytalZUSzucpSKGcw/wBcMnlN+xvUclARSW4b4M6y/+RtBZCLs BXPkjrJjHMgI3e8HcuA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE3MDAzMSBTYWx0ZWRfX+8v8eYoi6MDn TOMhqV5CXQ818h6Ah+BB8YvADU7fUXqvb2Q0mfolqavGVWKOK+4ya1LpoO42qHUGw0xdPECQjoM GYzoNf2/18vxyKsowTVfEAQjJx/MpgM= X-Authority-Analysis: v=2.4 cv=DYMnbPtW c=1 sm=1 tr=0 ts=6a59a4a2 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=zDMlSImzIToMmpLGiZwA:9 a=CjuIK1q_8ugA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: sNWcT16ueoWpCeKzLyjDYQM6g5JDCiAQ X-Proofpoint-ORIG-GUID: sNWcT16ueoWpCeKzLyjDYQM6g5JDCiAQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-17_01,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 adultscore=0 priorityscore=1501 spamscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607170031 On 26-07-17 01:56:59, Thinh Nguyen wrote: > On Thu, Jul 16, 2026, Peter Chen wrote: > > On 26-07-17 00:06:37, Thinh Nguyen wrote: > > > > > > > > I have seen fewer platforms use "phy_type" at dts for arm64, dwc3 > > > > core uses it only for special cases and the code was added for > > > > ten years ago. For the default situation, we may not need to > > > > change DWC3_GUSB2PHYCFG_EUSB2OPMODE value for UTMI+, Thinh, is it > > > > correct? > > > > > > > > > > The GUSB2PHYCFG.eUSB2OPMODE is only relevant for host mode and mainly > > > for electrical compliance. Usually by default, the CoreConsultant > > > setting should have this set correctly. So not explicitly setting it > > > should be functionally fine (IIRC). > > > > > > That said, this is separate from the GUSB2PHYCFG.PHYIF, which the core > > > uses dwc->hsphy_mode to indicate whether the UTMI interface is 8-bit or > > > 16-bit. > > > > > > > Why only rockchip uses this "phy_type" property, why other SoC vendors > > no this requirement for UTMI width setting? > > > > Not just rockchip, some tegra and hikey also use it. Some old qcom dts > files also have it for ulpi. Tegra and old qcom platforms use chipidea, hikey uses dwc3. > > It is typically set when the coreConsultant default differs from what > the platform needs, so the driver can override it with the correct > setting. > > My point is that changing "phy_type" definition is more involved than it > looks. I'm open to alternatives. > I know your concern that in case the eUSB2 PHY SoC wants to change UTMI width, it can't do that. Are there controller register know it connects eUSB2 PHY? For the place to put "eusb2" for phy type, I still think enum usb_phy_interface at: include/linux/usb/phy.h is the most suitable place, would you have any alternatives? Another solution is using generic PHY API phy_get_mode, set fixed "eusb2" mode at eUSB2 PHY driver, but it depends on PHY driver doesn't have different settings for device and host mode. Other solution is compare the generic PHY compatible string at dwc3 qcom glue layer, it depends on eUSB2 PHY compatible string always contains "eusb2-phy" I prefer the solution that extend enum usb_phy_interface for eUSB2 PHY, it uses existed kernel structure and device tree binding. -- Thanks, Peter Chen