From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755889Ab0EKUvQ (ORCPT ); Tue, 11 May 2010 16:51:16 -0400 Received: from nlpi129.sbcis.sbc.com ([207.115.36.143]:55171 "EHLO nlpi129.prodigy.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757959Ab0EKUvJ (ORCPT ); Tue, 11 May 2010 16:51:09 -0400 Date: Tue, 11 May 2010 15:46:59 -0500 (CDT) From: Christoph Lameter X-X-Sender: cl@router.home To: Mike Frysinger cc: Pekka Enberg , Matt Mackall , Dmitry Torokhov , Andrew Morton , Oskar Schirmer , Michael Hennerich , linux-input@vger.kernel.org, linux-kernel@vger.kernel.org, =?ISO-8859-15?Q?Daniel_Gl=F6ckner?= , Oliver Schneidewind , Johannes Weiner , Nick Piggin , David Rientjes , David Brownell , Grant Likely Subject: Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines In-Reply-To: Message-ID: References: <1273487642-2169-1-git-send-email-os@emlix.com> <20100511062110.GB9644@core.coreip.homeip.net> <20100511063309.GC9644@core.coreip.homeip.net> <1273608441.15067.1002.camel@calx> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 11 May 2010, Mike Frysinger wrote: > > DMA. If the arch can only DMA into cacheline aligned objects then the > > correct method is to force kmalloc alignment to cacheline size. > > these are SPI drivers and are usable on any arch that supports a SPI > bus (which is pretty much every arch). forget about "embedded" > arches. > > the issue here is simple: a SPI driver (AD7877) needs to do a receive > SPI transfer into a DMA safe buffer. what is the exact API to > dynamically allocate memory for the structure with this buffer > embedded in it such that the start of the structure is cached aligned > ? creating a dedicated kmem cache may work, but it isnt a scalable > solution if every SPI driver needs to create its own cache. kmalloc returns a pointer to a DMA safe buffer. There is no requirement on the x86 hardware that the DMA buffers have to be cache aligned. Cachelines will be invalidated as needed.