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Date: Tue, 11 Jun 2013 09:47:13 +0000 (UTC)
From: Paul Walmsley <pwalmsley@nvidia.com>
To: Prashant Gaikwad <pgaikwad@nvidia.com>
cc: Stephen Warren <swarren@wwwdotorg.org>,
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Subject: Re: [PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control
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On Tue, 11 Jun 2013, Prashant Gaikwad wrote:

> Why not implement these APIs in DFLL clock driver itself and pass RST address
> register to driver?

The DFLL DVCO reset registers are CAR registers, not DFLL registers.  
Functions that operate on registers in one IP block shouldn't be located 
in another IP block's driver.


- Paul