From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751891Ab3FYNRq (ORCPT ); Tue, 25 Jun 2013 09:17:46 -0400 Received: from www.linutronix.de ([62.245.132.108]:55802 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751803Ab3FYNRn (ORCPT ); Tue, 25 Jun 2013 09:17:43 -0400 Date: Tue, 25 Jun 2013 15:17:40 +0200 (CEST) From: Thomas Gleixner To: Srinivas KANDAGATLA cc: John Stultz , Grant Likely , Rob Herring , Rob Landley , devicetree-discuss@lists.ozlabs.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, Linus Walleij , Stuart Menefy , Arnd Bergmann , Rob Herring , Will Deacon Subject: Re: [PATCH v6] clocksource:arm_global_timer: Add ARM global timer support. In-Reply-To: <1372152678-29530-1-git-send-email-srinivas.kandagatla@st.com> Message-ID: References: <1372152678-29530-1-git-send-email-srinivas.kandagatla@st.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 25 Jun 2013, Srinivas KANDAGATLA wrote: > If its not too late can this patch be considered for 3.11 via clocksource tree? Sure. No worry, though I noticed a little detail when reading through it again. See below. > +/** > + * To ensure that updates to comparator value register do not set the > + * Interrupt Status Register proceed as follows: > + * 1. Clear the Comp Enable bit in the Timer Control Register. > + * 2. Write the lower 32-bit Comparator Value Register. > + * 3. Write the upper 32-bit Comparator Value Register. > + * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit. > + */ > +static void gt_compare_set(unsigned long delta, int periodic) > +{ > + u64 counter = gt_counter_read(); > + unsigned long ctrl = readl(gt_base + GT_CONTROL); Why are you reading the control register back over and over? All you need to preserve is the GT_CONTROL_TIMER_ENABLE bit. So you can spare that read out and just do ctrl = GT_CONTROL_TIMER_ENABLE; writel(ctrl, gt_base + GT_CONTROL); > +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id) > +{ > + struct clock_event_device *evt = dev_id; > + > + if (readl_relaxed(gt_base + GT_INT_STATUS) & > + GT_INT_STATUS_EVENT_FLAG) { If you negate the check and return IRQ_NONE, you save one indent level for the real code. > + /** > + * ERRATA 740657( Global Timer can send 2 interrupts for > + * the same event in single-shot mode) > + * Workaround: > + * Either disable single-shot mode. > + * Or > + * Modify the Interrupt Handler to avoid the > + * offending sequence. This is achieved by clearing > + * the Global Timer flag _after_ having incremented > + * the Comparator register value to a higher value. > + */ > + if (!(readl_relaxed(gt_base + GT_CONTROL) & > + GT_CONTROL_AUTO_INC)) Again, no need to read from the hardware. if (evt->mode == CLOCK_EVT_MODE_ONESHOT) tells you what you need to know. Thanks, tglx