From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932766AbcFJROt (ORCPT ); Fri, 10 Jun 2016 13:14:49 -0400 Received: from bastet.se.axis.com ([195.60.68.11]:35286 "EHLO bastet.se.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932227AbcFJROr (ORCPT ); Fri, 10 Jun 2016 13:14:47 -0400 Date: Fri, 10 Jun 2016 19:14:38 +0200 From: Ricard Wanderlof X-X-Sender: ricardw@lnxricardw1.se.axis.com To: Boris Brezillon CC: Brian Norris , David Woodhouse , Benoit Cousson , Tony Lindgren , , Linux mtd , Subject: Re: [PATCH 1/4] of: Add device tree bindings for Evatronix In-Reply-To: <20160610190357.5f10c00f@bbrezillon> Message-ID: References: <20160603162207.0688c9e6@bbrezillon> <20160608175018.16c88207@bbrezillon> <20160610175454.327f51a2@bbrezillon> <20160610190357.5f10c00f@bbrezillon> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-15" Content-Transfer-Encoding: 8BIT X-Originating-IP: [10.0.5.107] X-ClientProxiedBy: XBOX01.axis.com (10.0.5.15) To XBOX03.axis.com (10.0.5.17) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 10 Jun 2016, Boris Brezillon wrote: > > Basically, in the general case, the controller can handle a matrix of > > nand flash chips. There can be a number of banks, each of which can > > have a number of individual CS lines. For the (in this case academic) > > case of 3 banks and 4 chip selects per bank, there would be a total of > > 3 x 4 = 12 CS lines. > > > > For the IP configuration the driver was written for, there are only 2 > > CS lines, and we can configure if they are to be viewed by the > > controller as 2 CS lines within the same single bank, or 2 separate > > banks with one CS each. This is what the DT property is intended to > > express. It basically translates directly into a register write in the > > IP. > > Okay, got it. I guess we should just expose the chip select in a linear > way (3 banks of 4 CS means the controller should support up to 12 > chips), unless you really have a way to change the CS pins routing > internally. When I go through the driver I will also revisit this and give it some more thought if there's a set of bindings which would make sense both for the case we have now and for a general configuration of the IP. > > Yes, that makes sense of course, but what if someone would want to > > override the automatic settings, for whatever reason, using an > > optional DT property? I can think of several reasons either way, > > that's why I'm asking. > > You mean reducing the timings because the board design prevents using > the highest supported mode for example? That would actually be a valid > use case, and I guess we could make a generic property for that > (without the vendor prefix). Yes, either that, or if the automatic selection fails for some reason, say in a given case we know that the chips we are using support mode 2 timing, but one of them gets misidentified as mode 0. Sure, that is a bug and should be fixed of course, but I can imagine commercial situations where it may not be feasable to update the kernel, but where a new DT would be ok. /Ricard -- Ricard Wolf Wanderlöf ricardw(at)axis.com Axis Communications AB, Lund, Sweden www.axis.com Phone +46 46 272 2016 Fax +46 46 13 61 30