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Date: Fri, 5 Sep 2014 20:51:59 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Andrew Bresticker <abrestic@chromium.org>
cc: Ralf Baechle <ralf@linux-mips.org>, Rob Herring <robh+dt@kernel.org>,
        Pawel Moll <pawel.moll@arm.com>, Mark Rutland <mark.rutland@arm.com>,
        Ian Campbell <ijc+devicetree@hellion.org.uk>,
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        linux-mips@linux-mips.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 01/16] MIPS: Provide a generic plat_irq_dispatch
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On Fri, 5 Sep 2014, Andrew Bresticker wrote:
> For platforms which boot with device-tree and use the MIPS CPU interrupt
> controller binding, a generic plat_irq_dispatch() can be used since all
> CPU interrupts should be mapped through the CPU IRQ domain.  Implement a
> plat_irq_dispatch() which simply handles the highest pending interrupt.
> 
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Tested-by: Jonas Gorski <jogo@openwrt.org>
> ---
> No changes from v1.
> ---
>  arch/mips/kernel/irq_cpu.c | 28 +++++++++++++++++++++++-----
>  1 file changed, 23 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
> index e498f2b..9cf8459 100644
> --- a/arch/mips/kernel/irq_cpu.c
> +++ b/arch/mips/kernel/irq_cpu.c
> @@ -116,6 +116,24 @@ void __init mips_cpu_irq_init(void)
>  }
>  
>  #ifdef CONFIG_IRQ_DOMAIN
> +static struct irq_domain *mips_intc_domain;
> +
> +asmlinkage void __weak plat_irq_dispatch(void)
> +{
> +	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
> +	unsigned int hw;
> +	int irq;
> +
> +	if (!pending) {
> +		spurious_interrupt();
> +		return;
> +	}
> +
> +	hw = fls(pending) - CAUSEB_IP - 1;
> +	irq = irq_linear_revmap(mips_intc_domain, hw);
> +	do_IRQ(irq);

Why are you not handling all pending interrupts in a loop?

Thanks,

	tglx