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Date: Fri, 31 Oct 2014 16:34:25 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
To: Juergen Gross <jgross@suse.com>
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Subject: Re: [PATCH 10/17] x86: Use new cache mode type in setting page
 attributes
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On Fri, 31 Oct 2014, Juergen Gross wrote:
> --- a/arch/x86/mm/pageattr.c
> +++ b/arch/x86/mm/pageattr.c
> @@ -1304,12 +1304,6 @@ static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
>  	return 0;
>  }
>  
> -static inline int cache_attr(pgprot_t attr)
> -{
> -	return pgprot_val(attr) &
> -		(_PAGE_PAT | _PAGE_PAT_LARGE | _PAGE_PWT | _PAGE_PCD);
> -}
> -
>  static int change_page_attr_set_clr(unsigned long *addr, int numpages,
>  				    pgprot_t mask_set, pgprot_t mask_clr,
>  				    int force_split, int in_flag,
> @@ -1390,7 +1384,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
>  	 * No need to flush, when we did not set any of the caching
>  	 * attributes:
>  	 */
> -	cache = cache_attr(mask_set);
> +	cache = !!pgprot2cachemode(mask_set);

So this loses _PAGE_PAT_LARGE, right ?

>  int set_memory_uc(unsigned long addr, int numpages)
> @@ -1456,7 +1451,7 @@ int set_memory_uc(unsigned long addr, int numpages)
>  	 * for now UC MINUS. see comments in ioremap_nocache()
>  	 */
>  	ret = reserve_memtype(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
> -			    _PAGE_CACHE_UC_MINUS, NULL);
> +			      _PAGE_CACHE_UC_MINUS, NULL);

That should be in the patch which added the _PAGE_CACHE_UC_MINUS

>  int _set_memory_wb(unsigned long addr, int numpages)
>  {
> +	/* WB cache mode is hard wired to all cache attribute bits being 0 */

I like the comment, but shouldn't we compile time check that
assumption somewhere?

>  	return change_page_attr_clear(&addr, numpages,
>  				      __pgprot(_PAGE_CACHE_MASK), 0);

Thanks,

	tglx