From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758682AbaJaU3U (ORCPT ); Fri, 31 Oct 2014 16:29:20 -0400 Received: from www.linutronix.de ([62.245.132.108]:45527 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750886AbaJaU3T (ORCPT ); Fri, 31 Oct 2014 16:29:19 -0400 Date: Fri, 31 Oct 2014 21:28:59 +0100 (CET) From: Thomas Gleixner To: Borislav Petkov cc: Juergen Gross , hpa@zytor.com, x86@kernel.org, mingo@redhat.com, stefan.bader@canonical.com, linux-kernel@vger.kernel.org, xen-devel@lists.xensource.com, konrad.wilk@oracle.com, ville.syrjala@linux.intel.com, david.vrabel@citrix.com, jbeulich@suse.com, toshi.kani@hp.com, plagnioj@jcrosoft.com, tomi.valkeinen@ti.com, bhelgaas@google.com Subject: Re: [PATCH 01/17] x86: Make page cache mode a real type In-Reply-To: <20141031194207.GA15367@pd.tnic> Message-ID: References: <1414764033-30011-1-git-send-email-jgross@suse.com> <1414764033-30011-2-git-send-email-jgross@suse.com> <20141031194207.GA15367@pd.tnic> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001,URIBL_BLOCKED=0.001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 31 Oct 2014, Borislav Petkov wrote: > On Fri, Oct 31, 2014 at 03:00:17PM +0100, Juergen Gross wrote: > > At the moment there are a lot of places that handle setting or getting > > the page cache mode by treating the pgprot bits equal to the cache mode. > > This is only true because there are a lot of assumptions about the setup > > of the PAT MSR. Otherwise the cache type needs to get translated into > > pgprot bits and vice versa. > > > > This patch tries to prepare for that by introducing a separate type > > for the cache mode and adding functions to translate between those and > > pgprot values. > > > > To avoid too much performance penalty the translation between cache mode > > and pgprot values is done via tables which contain the relevant > > information. Write-back cache mode is hard-wired to be 0, all other > > modes are configurable via those tables. For large pages there are > > translation functions as the PAT bit is located at different positions > > in the ptes of 4k and large pages. > > > > Signed-off-by: Stefan Bader > > Signed-off-by: Juergen Gross > > Just a clarification question: how is one to understand this attribution > here? Is Stefan the original author, was he a reviewer, or? Because this > SOB chain is misleading... Bah, wanted to ask that as well. Then got lost in the review and forgot.... Thanks, tglx