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Date: Sat, 24 Jan 2015 20:24:26 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
To: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
cc: Russell King <linux@arm.linux.org.uk>, Jason Cooper <jason@lakedaemon.net>,
        Linus Walleij <linus.walleij@linaro.org>,
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Subject: Re: [PATCH 3/5] ARM: sa1100: use ioremapped memory to access SC
 registers
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On Sat, 24 Jan 2015, Dmitry Eremin-Solenikov wrote:

> 2015-01-24 20:48 GMT+03:00 Thomas Gleixner <tglx@linutronix.de>:
> > On Thu, 15 Jan 2015, Dmitry Eremin-Solenikov wrote:
> >>  static void sa1100_mask_irq(struct irq_data *d)
> >>  {
> >> -     ICMR &= ~BIT(d->hwirq);
> >> +     u32 reg;
> >> +     unsigned long flags;
> >> +
> >> +     raw_spin_lock_irqsave(&lock, flags);
> >
> > What's the exact point of that lock? And how is it related to the
> > $subject of the patch?
> 
> It is needed to protect ICMR register during RMW cycle, isn't it?

The original code has no protection for the RMW either.

And there is a simple reason for this. These functions are guaranteed
to be called with interrupts disabled and this is a uniprocessor
machine and it will never grow SMP support. So interrupts disabled is
serialization enough.

Thanks,

	tglx