From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755956AbbGFPrx (ORCPT ); Mon, 6 Jul 2015 11:47:53 -0400 Received: from www.linutronix.de ([62.245.132.108]:55953 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754582AbbGFPrs (ORCPT ); Mon, 6 Jul 2015 11:47:48 -0400 Date: Mon, 6 Jul 2015 17:47:40 +0200 (CEST) From: Thomas Gleixner To: Ingo Molnar cc: Andy Shevchenko , x86@kernel.org, Aubrey Li , "Rafael J . Wysocki" , "Kumar P, Mahesh" , linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org Subject: Re: [PATCH v3 4/5] x86: pmc_atom: Add Cherrytrail PMC interface In-Reply-To: <20150706154425.GA19665@gmail.com> Message-ID: References: <1436192944-56496-1-git-send-email-andriy.shevchenko@linux.intel.com> <1436192944-56496-5-git-send-email-andriy.shevchenko@linux.intel.com> <20150706154425.GA19665@gmail.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001,URIBL_BLOCKED=0.001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 6 Jul 2015, Ingo Molnar wrote: > * Andy Shevchenko wrote: > > > The patch adds CHT PMC interface. This exposes all the South IP device power > > states and S0ix states for CHT. The bit map of FUNC_DIS and D3_STS_0 registers > > for SoCs are consistent. The D3_STS_1 and FUNC_DIS_2 registers, however, are > > not aligned. This is fixed by splitting a common mapping on per register basis. > > > > Signed-off-by: Kumar P Mahesh > > Signed-off-by: Andy Shevchenko > > That's a weird signoff sequence. I changed it to: > > Signed-off-by: Andy Shevchenko > Acked-by: Kumar P Mahesh It might lack a From: Kumar ...