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From: Thomas Gleixner <tglx@linutronix.de>
To: Toshi Kani <toshi.kani@hp.com>
Cc: Jan Beulich <JBeulich@suse.com>,
	peterz@infradead.org, mingo@kernel.org, x86@kernel.org,
	bp@suse.de, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86, pat: Add comments to cachemode translation tables
Date: Sun, 2 Aug 2015 12:07:25 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.11.1508021206430.3825@nanos> (raw)
In-Reply-To: <1437665929.3214.313.camel@hp.com>

On Thu, 23 Jul 2015, Toshi Kani wrote:
> On Thu, 2015-07-23 at 09:36 -0600, Jan Beulich wrote:
> > > 
> > > > > On 23.07.15 at 17:25, <toshi.kani@hp.com> wrote:
> > > Yes, I agree with you.  But such risk is very low -- 1) the regular 
> > > case
> > > (no fallback) is used most of the cases, 2) the code using WT knows 
> > > what
> > > type of memory it is dealing with.  For example, pmem may map NVDIMM 
> > > with
> > > WT, and any sane BIOS sets MTRR to WB for NVDIMM. 
> > 
> > Do the words "sane" and "BIOS" really fit together in your opinion?
> 
> :-)
> 
> Anyway, I am not disagreeing with you... When UC is ready for both regular
> memory and IO memory, it should be changed to fall back to UC.

What's the resolution of this discussion? Is that patch correct as is
or do we get an updated version?

Thanks,

	tglx

  reply	other threads:[~2015-08-02 10:07 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-07-22 18:06 Toshi Kani
2015-07-23  6:42 ` Jan Beulich
2015-07-23 14:27   ` Toshi Kani
2015-07-23 14:50     ` Jan Beulich
2015-07-23 15:25       ` Toshi Kani
2015-07-23 15:36         ` Jan Beulich
2015-07-23 15:38           ` Toshi Kani
2015-08-02 10:07             ` Thomas Gleixner [this message]
2015-08-03 15:08               ` Toshi Kani
2015-08-20 19:30 ` [tip:x86/mm] x86/mm/pat: " tip-bot for Toshi Kani

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