From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753905AbbHRQrb (ORCPT ); Tue, 18 Aug 2015 12:47:31 -0400 Received: from www.linutronix.de ([62.245.132.108]:57552 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753781AbbHRQra (ORCPT ); Tue, 18 Aug 2015 12:47:30 -0400 Date: Tue, 18 Aug 2015 18:46:51 +0200 (CEST) From: Thomas Gleixner To: Tim Chen cc: Dave Hansen , Ingo Molnar , "H. Peter Anvin" , Herbert Xu , Chandramouli Narayanan , x86@kernel.org, linux-kernel@vger.kernel.org, Borislav Petkov , mouli_7982@yahoo.com Subject: Re: [PATCH] sha: Enable cpuid check for Intel SHA extensions implementations In-Reply-To: <1439850820.21627.11.camel@schen9-desk2.jf.intel.com> Message-ID: References: <1439844283.21627.5.camel@schen9-desk2.jf.intel.com> <55D24FEA.1000803@intel.com> <1439850820.21627.11.camel@schen9-desk2.jf.intel.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001,URIBL_BLOCKED=0.001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 17 Aug 2015, Tim Chen wrote: > Signed-off-by: Chandramouli Narayanan > Signed-off-by: Tim Chen And now the question who authored this complex one liner .... > --- > arch/x86/include/asm/cpufeature.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > index 3d6606f..a94f83d 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -239,6 +239,7 @@ > #define X86_FEATURE_AVX512PF ( 9*32+26) /* AVX-512 Prefetch */ > #define X86_FEATURE_AVX512ER ( 9*32+27) /* AVX-512 Exponential and Reciprocal */ > #define X86_FEATURE_AVX512CD ( 9*32+28) /* AVX-512 Conflict Detection */ > +#define X86_FEATURE_SHA_NI ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */ > > /* Extended state features, CPUID level 0x0000000d:1 (eax), word 10 */ > #define X86_FEATURE_XSAVEOPT (10*32+ 0) /* XSAVEOPT */ > -- > 1.8.3.1 > > > >