From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753252AbbI3ODn (ORCPT ); Wed, 30 Sep 2015 10:03:43 -0400 Received: from www.linutronix.de ([62.245.132.108]:37064 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750947AbbI3ODm (ORCPT ); Wed, 30 Sep 2015 10:03:42 -0400 Date: Wed, 30 Sep 2015 16:03:01 +0200 (CEST) From: Thomas Gleixner To: Qais Yousef cc: Jiang Liu , linux-kernel@vger.kernel.org, marc.zyngier@arm.com, jason@lakedaemon.net, linux-mips@linux-mips.org Subject: Re: [PATCH 0/6] Implement generic IPI support mechanism In-Reply-To: <560BE4F3.7060607@imgtec.com> Message-ID: References: <1443019758-20620-1-git-send-email-qais.yousef@imgtec.com> <5602D958.6000003@linux.intel.com> <5603B6CA.7050601@imgtec.com> <560BE4F3.7060607@imgtec.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 30 Sep 2015, Qais Yousef wrote: > On 09/29/2015 09:48 PM, Thomas Gleixner wrote: > > > > Now how these hwirqs are allocated is a domain/architecture > > specific issue. > > > > x86 will just find a vector which is available on all target > > cpus and mark it as used. That's a single hw irq number. > > > > mips and others, which implement IPIs as regular hw interrupt > > numbers, will allocate a these (consecutive) hw interrupt > > numbers either from a reserved region or just from the > > regular space. That's a bunch of hw irq numbers and we need > > to come up with a proper storage format in the irqdata for > > that. That might be > > > > struct ipi_mapping { > > unsigned int nr_hwirqs; > > unsigned int cpumap[NR_CPUS]; > > }; > > Can we use NR_CPUS here? If we run in UP configuration for instance, this will > be one. The coprocessor could be outside the NR_CPUS range in general, no? > > How about > > struct ipi_mapping { > unsigned int nr_hwirqs; > unsigned int nr_cpus; > unsigned int *cpumap; > } > > where cpumap is dynamically allocated by the controller which has better > knowledge about the supported cpu range it can talk to? Sure. As I said: 'That might be' .... Thanks, tglx