From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756126AbbJALCD (ORCPT ); Thu, 1 Oct 2015 07:02:03 -0400 Received: from www.linutronix.de ([62.245.132.108]:60320 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753830AbbJALCB (ORCPT ); Thu, 1 Oct 2015 07:02:01 -0400 Date: Thu, 1 Oct 2015 13:01:19 +0200 (CEST) From: Thomas Gleixner To: Dave Hansen cc: borntraeger@de.ibm.com, x86@kernel.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, dave.hansen@linux.intel.com Subject: Re: [PATCH 01/25] x86, fpu: add placeholder for Processor Trace XSAVE state In-Reply-To: <20150928191818.34AAC17E@viggo.jf.intel.com> Message-ID: References: <20150928191817.035A64E2@viggo.jf.intel.com> <20150928191818.34AAC17E@viggo.jf.intel.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001,URIBL_BLOCKED=0.001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 28 Sep 2015, Dave Hansen wrote: > From: Dave Hansen > > There is an XSAVE state component for Intel Processor Trace. But, > we do not use it and do not expect to ever use it. > > We add a placeholder in the code for it so it is not a mystery and > also so we do not need an explicit enum initialization for Protection > Keys in a moment. > > Why will we never use it? According to Andi Kleen: > > The XSAVE support assumes that there is a single buffer > for each thread. But perf generally doesn't work this > way, it usually has only a single perf event per CPU per > user, and when tracing multiple threads on that CPU it > inherits perf event buffers between different threads. So > XSAVE per thread cannot handle this inheritance case > directly. > > Using multiple XSAVE areas (another one per perf event) > would defeat some of the state caching that the CPUs do. > > Signed-off-by: Dave Hansen Reviewed-by: Thomas Gleixner