From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751741AbbJKJzd (ORCPT ); Sun, 11 Oct 2015 05:55:33 -0400 Received: from www.linutronix.de ([62.245.132.108]:41442 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751635AbbJKJz3 (ORCPT ); Sun, 11 Oct 2015 05:55:29 -0400 Date: Sun, 11 Oct 2015 11:54:49 +0200 (CEST) From: Thomas Gleixner To: Marc Zyngier cc: "majun (F)" , Catalin.Marinas@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Will.Deacon@arm.com, mark.rutland@arm.com, jason@lakedaemon.net, lizefan@huawei.com, huxinwei@huawei.com, dingtianhong@huawei.com, zhaojunhua@hisilicon.com, liguozhu@hisilicon.com, xuwei5@hisilicon.com, wei.chenwei@hisilicon.com, guohanjun@huawei.com, wuyun.wu@huawei.com, guodong.xu@linaro.org, haojian.zhuang@linaro.org, zhangfei.gao@linaro.org, usman.ahmad@linaro.org, klimov.linux@gmail.com Subject: Re: [PATCH v5 1/3] initialize each mbigen device node as a interrupt controller. In-Reply-To: <20151010110942.52d34a4b@arm.com> Message-ID: References: <1443605949-15396-1-git-send-email-majun258@huawei.com> <1443605949-15396-2-git-send-email-majun258@huawei.com> <5610D3BD.1040408@huawei.com> <5618D3EC.6050501@huawei.com> <20151010110942.52d34a4b@arm.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 10 Oct 2015, Marc Zyngier wrote: > On Sat, 10 Oct 2015 17:01:32 +0800 > "majun (F)" wrote: > > But there is a problem If i make the structure like you said. > > > > For example, my hardware structure likes below: > > > > uart ------> mbigen --> ITS-pMSI --> ITS --> GIC > > virq1 > > > > virq1 means the virq number allocted by irq_of_parse_and_map() function > > when system parse the uart dts node in initializing stage. > > > > To create a ITS device, I need to call msi_domain_alloc_irqs() function > > in my mbigen alloc function. > > > > In this function, a new virq number(named as virq2 ) which different from > > virq1 is allocated. > > So, this is a big problem. > > I think I see what your problem is: > - The wired interrupt (uart -> mbigen) is allocated through DT (and > must be available early, because of of_platform_populate), > - The MSI (mgigen -> ITS) is dynamic (and allocated much later, > because the device model kicks in after irqchip init, and we cannot > allocate MSIs without a device). Why do we need that wired interrupt at all? We can make mbigen the 'msi-parent' of the device and let the msi_domain_ops::msi_prepare() callback figure out the actual wiring through device->fwnode. Thanks, tglx