From: Thomas Gleixner <tglx@linutronix.de>
To: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-kernel@vger.kernel.org, jason@lakedaemon.net,
marc.zyngier@arm.com, jiang.liu@linux.intel.com,
ralf@linux-mips.org, linux-mips@linux-mips.org
Subject: Re: [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domaind
Date: Fri, 20 Nov 2015 21:39:21 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.11.1511202113010.3931@nanos> (raw)
In-Reply-To: <564EFA74.90606@imgtec.com>
Qais,
On Fri, 20 Nov 2015, Qais Yousef wrote:
> On 11/16/2015 05:17 PM, Thomas Gleixner wrote:
> > 1) IPI as per_cpu interrupts
> >
> > Single hwirq represented by a single irq descriptor
> >
> > 2) IPI with consecutive mapping space
> >
> > No extra mapping from virq base to target cpu required as its just
> > linear. Everything can be handled via the base virq.
> >
>
>
> I think I am seeing a major issue with this approach.
>
> Take the case where we reserve an IPI with ipi_mask that has cpu 5 and 6 set
> only. When allocating a per_cpu or consectuve mapping, we will require 2
> consecutive virqs and hwirqs. But since the cpu location is not starting from
> 0, we can't use the cpu as an offset anymore.
>
> So when a user wants to send an IPI to cpu 6 only, the code can't easily tell
> what's the correct offset from base virq or hwirq to use.
Well, you can store the start offset easily and subtract it. It's 0
for most of the cases.
> Same applies when doing the reverse mapping.
>
> In other words, the ipi_mask won't always necessarily be linear to facilitate
> the 1:1 mapping that this approach assumes.
>
> It is a solvable problem, but I think we're losing the elegance that promoted
> going into this direction and I think sticking to using struct ipi_mapping
> (with some enhancements to how it's exposed an integrated by/into generic
> code) is a better approach.
The only reason to use the ipi_mapping thing is if we need non
consecutive masks, i.e. cpu 5 and 9.
I really don't want to have it mandatory as it does not make any sense
for systems where the IPI is a single per_cpu interrupt. For the
linear consecutive space it is just adding memory and cache footprint
for no benefit. Think about machines with 4k and more cpus ....
If you make ipi_mapping in a way that it can express the per_cpu,
linear and scattered mappings, then we should be fine. The extra
conditional you need in send_ipi() is not a problem.
Thanks,
tglx
next prev parent reply other threads:[~2015-11-20 20:40 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-11-03 11:12 [PATCH 00/14] Implement generic IPI support mechanism Qais Yousef
2015-11-03 11:12 ` [PATCH 01/14] genirq: Add new IRQ_DOMAIN_FLAGS_IPI Qais Yousef
2015-11-03 11:12 ` [PATCH 02/14] genirq: Add DOMAIN_BUS_IPI Qais Yousef
2015-11-03 11:12 ` [PATCH 03/14] genirq: Add GENERIC_IRQ_IPI Kconfig symbol Qais Yousef
2015-11-03 11:12 ` [PATCH 04/14] genirq: Add new struct ipi_mask and helper functions Qais Yousef
2015-11-07 12:05 ` Thomas Gleixner
2015-11-03 11:12 ` [PATCH 05/14] genirq: Add struct ipi_mask to irq_data Qais Yousef
2015-11-03 11:12 ` [PATCH 06/14] genirq: Add struct ipi_mapping and its helper functions Qais Yousef
2015-11-07 12:09 ` Thomas Gleixner
2015-11-09 10:05 ` Qais Yousef
2015-11-03 11:12 ` [PATCH 07/14] genirq: Add a new generic IPI reservation code to irq core Qais Yousef
2015-11-03 12:06 ` kbuild test robot
2015-11-07 12:11 ` Thomas Gleixner
2015-11-07 13:31 ` Thomas Gleixner
2015-11-09 10:07 ` Qais Yousef
2015-11-16 15:09 ` Thomas Gleixner
2015-11-03 11:12 ` [PATCH 08/14] genirq: Add a new irq_send_ipi() to irq_chip Qais Yousef
2015-11-03 11:12 ` [PATCH 09/14] genirq: Implement irq_send_ipi() to be used by drivers Qais Yousef
2015-11-03 12:09 ` kbuild test robot
2015-11-07 12:14 ` Thomas Gleixner
2015-11-03 11:12 ` [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain Qais Yousef
2015-11-07 14:51 ` Thomas Gleixner
2015-11-09 11:10 ` Qais Yousef
2015-11-16 17:17 ` Thomas Gleixner
2015-11-17 10:08 ` Qais Yousef
2015-11-17 10:11 ` Thomas Gleixner
2015-11-17 10:30 ` Qais Yousef
2015-11-20 10:48 ` Qais Yousef
2015-11-20 20:39 ` Thomas Gleixner [this message]
2015-11-23 16:55 ` [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domaind Qais Yousef
2015-11-12 15:12 ` [PATCH 10/14] irqchip/mips-gic: Add a IPI hierarchy domain Qais Yousef
2015-11-16 17:24 ` Thomas Gleixner
2015-11-17 10:24 ` Qais Yousef
2015-11-17 10:30 ` Thomas Gleixner
2015-11-03 11:12 ` [PATCH 11/14] MIPS: Add generic SMP IPI support Qais Yousef
2015-11-03 11:12 ` [PATCH 12/14] MIPS: Make smp CMP, CPS and MT use the new generic IPI functions Qais Yousef
2015-11-03 11:13 ` [PATCH 13/14] MIPS: Delete smp-gic.c Qais Yousef
2015-11-03 11:13 ` [PATCH 14/14] Docs: IRQ: Add new IRQ-ipi.txt Qais Yousef
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