From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752809AbcBBNgW (ORCPT ); Tue, 2 Feb 2016 08:36:22 -0500 Received: from www.linutronix.de ([62.245.132.108]:49215 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751159AbcBBNgV (ORCPT ); Tue, 2 Feb 2016 08:36:21 -0500 Date: Tue, 2 Feb 2016 14:35:12 +0100 (CET) From: Thomas Gleixner To: Noam Camus cc: linux-kernel@vger.kernel.org, linux-snps-arc@lists.infradead.org, daniel.lezcano@linaro.org, marc.zyngier@arm.com, cmetcalf@ezchip.com, talz@ezchip.com, giladb@ezchip.com, Jason Cooper Subject: Re: [PATCH v2 3/3] irqchip: add nps Internal and external irqchips In-Reply-To: <1454418899-25500-4-git-send-email-noamc@ezchip.com> Message-ID: References: <1454418899-25500-1-git-send-email-noamc@ezchip.com> <1454418899-25500-4-git-send-email-noamc@ezchip.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 2 Feb 2016, Noam Camus wrote: > +#include > +#include > +#include > +#include > +#include > +#include > + > +#undef NR_CPU_IRQS What's that #undef for? > +#define NR_CPU_IRQS 8 /* number of interrupt lines of NPS400 CPU */ > +#define TIMER0_IRQ 3 > +static void nps400_irq_eoi_global(struct irq_data *irqd) > +{ > + unsigned int __maybe_unused irq = irqd_to_hwirq(irqd); > + > + write_aux_reg(CTOP_AUX_IACK, 1 << irq); > + > + /* Don't ack before all device access attempts are done */ > + mb(); And what is that memory barrier for if this is not on ARC? > + > +#ifdef __arc__ > + __asm__ __volatile__ ( > + " .word %0\n" First of all this wants to be .inst not .word. > + : > + : "i"(CTOP_INST_RSPI_GIC_0_R12) > + : "memory"); And this needs be defined as an inline somewhere in arch/arc and not in the driver. In the driver you do: #ifdef CONFIG_ARCH_ARC # include #else static inline void arc_ack_gic(void) { } #endif static void nps400_irq_eoi_global { .... arc_ack_gic(); } Hmm? > +static int nps400_irq_map(struct irq_domain *d, unsigned int virq, > + irq_hw_number_t hw) > +{ > + switch (hw) { > + case TIMER0_IRQ: > +#ifdef CONFIG_SMP > + case IPI_IRQ: > +#endif > + irq_set_percpu_devid(virq); > + irq_set_chip_and_handler(virq, &nps400_irq_chip_percpu, > + handle_percpu_devid_irq); > + break; break; Please > + default: > + irq_set_chip_and_handler(virq, &nps400_irq_chip_fasteoi, > + handle_fasteoi_irq); > + break; Ditto. Thanks, tglx