mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Thomas Gleixner <tglx@linutronix.de>
To: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org,
	linux-kernel@vger.kernel.org,
	David Daney <david.daney@cavium.com>,
	Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Ian Campbell <ijc+devicetree@hellion.org.uk>,
	Kumar Gala <galak@codeaurora.org>,
	devicetree@vger.kernel.org
Subject: Re: [PATCH 6/7] [PATCH] MIPS: OCTEON: Add support for OCTEON III interrupt controller.
Date: Fri, 5 Feb 2016 10:06:34 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.11.1602050954480.25254@nanos> (raw)
In-Reply-To: <1454632974-7686-7-git-send-email-ddaney.cavm@gmail.com>

On Thu, 4 Feb 2016, David Daney wrote:
> +static int octeon_irq_ciu_set_type(struct irq_data *data, unsigned int t)
> +{
> +	irqd_set_trigger_type(data, t);
> +
> +	if (irqd_get_trigger_type(data) & IRQ_TYPE_EDGE_BOTH)
> +		irq_set_handler_locked(data, handle_edge_irq);
> +	else
> +		irq_set_handler_locked(data, handle_level_irq);
> +
> +	return IRQ_SET_MASK_OK;

That doesn't make any sense. First you store the type 't' in irq data, then
you query irq data for the type and at the end you tell the core to set the
type in irq data.

     if (t & IRQ_TYPE_EDGE_BOTH)
     	...
     else
        ...
     return IRQ_SET_MASK_OK;

does the same, right?

> +int octeon_irq_ciu3_xlat(struct irq_domain *d,

static ?

> +			 struct device_node *node,
> +			 const u32 *intspec,
> +			 unsigned int intsize,
> +			 unsigned long *out_hwirq,
> +			 unsigned int *out_type)
> +{
> +
> +void octeon_irq_ciu3_enable(struct irq_data *data)

static 

> +void octeon_irq_ciu3_disable(struct irq_data *data)
> +void octeon_irq_ciu3_ack(struct irq_data *data)
> +void octeon_irq_ciu3_mask(struct irq_data *data)
> +void octeon_irq_ciu3_mask_ack(struct irq_data *data)
> +int octeon_irq_ciu3_set_affinity(struct irq_data *data,
> +				 const struct cpumask *dest, bool force)

ditto

> +int octeon_irq_ciu3_mapx(struct irq_domain *d, unsigned int virq,
> +			 irq_hw_number_t hw, struct irq_chip *chip)

....

> +void octeon_ciu3_mbox_send(int cpu, unsigned int mbox)
> +{
> +	struct octeon_ciu3_info *ciu3_info;
> +	unsigned int intsn;
> +	union cvmx_ciu3_iscx_w1s isc_w1s;
> +	u64 isc_w1s_addr;
> +
> +	if (WARN_ON_ONCE(mbox >= CIU3_MBOX_PER_CORE))
> +		return;
> +
> +	intsn = octeon_irq_ciu3_mbox_intsn_for_cpu(cpu, mbox);
> +	ciu3_info = per_cpu(octeon_ciu3_info, cpu);
> +	isc_w1s_addr = ciu3_info->ciu3_addr + CIU3_ISC_W1S(intsn);
> +
> +	isc_w1s.u64 = 0;
> +	isc_w1s.s.raw = 1;
> +
> +	cvmx_write_csr(isc_w1s_addr, isc_w1s.u64);
> +	cvmx_read_csr(isc_w1s_addr);
> +}
> +EXPORT_SYMBOL(octeon_ciu3_mbox_send);

Why need modules that function?

Thanks,

	tglx

  reply	other threads:[~2016-02-05  9:07 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-02-05  0:42 [PATCH 0/7] MIPS: Add support for OCTEON cn78xx and cn73xx David Daney
2016-02-05  0:42 ` [PATCH 1/7] MIPS: OCTEON: Remove some code limiting NR_IRQS to 255 David Daney
2016-02-05  0:42 ` [PATCH 2/7] MIPS: Select CONFIG_HANDLE_DOMAIN_IRQ and make it work David Daney
2016-02-05  0:42 ` [PATCH 3/7] MIPS: OCTEON: Add register definitions for cn73xx, cnf75xx and cn78xx David Daney
2016-02-05  0:42 ` [PATCH 4/7] MIPS: OCTEON: Add model checking support " David Daney
2016-02-05  0:42 ` [PATCH 5/7] MIPS: OCTEON: Don't attempt to use nonexistent registers on OCTEON III models David Daney
2016-02-05  0:42 ` [PATCH 6/7] [PATCH] MIPS: OCTEON: Add support for OCTEON III interrupt controller David Daney
2016-02-05  9:06   ` Thomas Gleixner [this message]
2016-02-05 17:22     ` David Daney
2016-02-08 10:38       ` Thomas Gleixner
2016-02-08 19:14   ` Rob Herring
2016-02-05  0:42 ` [PATCH 7/7] MIPS: OCTEON: Add SMP support for OCTEON cn78xx et al David Daney
2016-02-05  1:22 ` [PATCH 0/7] MIPS: Add support for OCTEON cn78xx and cn73xx Aaro Koskinen
2016-02-05  1:31   ` David Daney

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=alpine.DEB.2.11.1602050954480.25254@nanos \
    --to=tglx@linutronix.de \
    --cc=david.daney@cavium.com \
    --cc=ddaney.cavm@gmail.com \
    --cc=devicetree@vger.kernel.org \
    --cc=galak@codeaurora.org \
    --cc=ijc+devicetree@hellion.org.uk \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mips@linux-mips.org \
    --cc=mark.rutland@arm.com \
    --cc=pawel.moll@arm.com \
    --cc=ralf@linux-mips.org \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®