From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758150AbcEFJtR (ORCPT ); Fri, 6 May 2016 05:49:17 -0400 Received: from www.linutronix.de ([62.245.132.108]:58483 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757924AbcEFJtO (ORCPT ); Fri, 6 May 2016 05:49:14 -0400 Date: Fri, 6 May 2016 11:47:19 +0200 (CEST) From: Thomas Gleixner To: Chen Yu cc: x86@kernel.org, linux-kernel@vger.kernel.org, Ingo Molnar , "H. Peter Anvin" , Bin Gao , Len Brown , "Rafael J. Wysocki" , "3 . 14+ # 3 . 14+" Subject: Re: [PATCH] x86, tsc: Fix tsc ratio calibration to avoid broken mdelay In-Reply-To: <1462505619-5516-1-git-send-email-yu.c.chen@intel.com> Message-ID: References: <1462505619-5516-1-git-send-email-yu.c.chen@intel.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 6 May 2016, yu.c.chen@intel.com wrote: > From: Chen Yu > > Currently we fetch the tsc radio by: > ratio = (lo >> 8) & 0x1f; > thus get bit8~bit12 of the MSR_PLATFORM_INFO, however according > to Intel 64 and IA-32 Architectures Software Developer Manual 35.5, > the ratio bit should be bit8~bit15, otherwise we might get incorrect > tsc ratio and cause system hang later(mdelay corrupted). The resulting issue is that both TSC frequency, which is used for udelay, and the lapic timer frequency are wrong. mdelay is just the visible damage caused by that. Thanks, tglx