From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754631AbcHXIzn (ORCPT ); Wed, 24 Aug 2016 04:55:43 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:59090 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753964AbcHXIz1 (ORCPT ); Wed, 24 Aug 2016 04:55:27 -0400 Date: Wed, 24 Aug 2016 10:51:20 +0200 (CEST) From: Thomas Gleixner To: Bin Gao cc: Ingo Molnar , "H. Peter Anvin" , x86@kernel.org, linux-kernel@vger.kernel.org, bin.gao@intel.com Subject: Re: [PATCH v2] x86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined calibration In-Reply-To: <20160816174240.GA33372@worksta> Message-ID: References: <20160816174240.GA33372@worksta> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 16 Aug 2016, Bin Gao wrote: > On some newer Intel x86 processors/SoCs the TSC frequency can be directly > calculated by factors read from specific MSR registers or from a cpuid > leaf (0x15). TSC frequency calculated by native msr/cpuid is absolutely > accurate so we should always skip calibrating TSC aginst another clock, > e.g. PIT, HPET, etc. So we want to skip the refined calibration by setting > the X86_FEATURE_TSC_RELIABLE flag. Existing code setting the flag by > set_cpu_cap() doesn't work as the flag is cleared later in identify_cpu(). > A cpu caps flag is not cleared only if it's set by setup_force_cpu_cap(). > This patch converted set_cpu_cap() to setup_force_cpu_cap() to ensure > refined calibration is skipped. > > We had a test on Intel CherryTrail platform: the 24 hours time drift is > 3.6 seconds if refined calibration was not skipped while the drift is less > than 0.6 second when refined calibration was skipped. > > Correctly setting the X86_FEATURE_TSC_RELIABLE flag also guarantees TSC is > not monitored by timekeeping watchdog because on most of these system TSC > is the only reliable clocksource. HPET, for instance, works but may not > be reliable. So kernel may report a physically reliable TSC is not reliable > just because a physically not reliable HPET is acting as timekeeping > watchdog. What about non SoC systems where the MSR is available, but we still see that cross socket TSC wreckage? This change will prevent the watchdog from detecting that. Thanks, tglx