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Date: Tue, 6 Sep 2016 17:50:14 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Waiman Long <Waiman.Long@hpe.com>
cc: Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
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        Scott J Norton <scott.norton@hpe.com>,
        Douglas Hatch <doug.hatch@hpe.com>, Randy Wright <rwright@hpe.com>
Subject: Re: [RESEND PATCH v6] x86/hpet: Reduce HPET counter read
 contention
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On Tue, 6 Sep 2016, Waiman Long wrote:
> 
> This is done by using a combination word with a sequence number and
> a bit lock. The CPU that gets the bit lock will be responsible for
> reading the HPET counter and update the sequence number. The others
> will monitor the change in sequence number and grab the HPET counter
> value accordingly. This change is only enabled on SMP configuration.

That hardly matches the implementation.
 
Thanks,

	tglx