From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S934942AbcJQLFs (ORCPT <rfc822;w@1wt.eu>);
        Mon, 17 Oct 2016 07:05:48 -0400
Received: from Galois.linutronix.de ([146.0.238.70]:36716 "EHLO
        Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S932761AbcJQLFk (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Mon, 17 Oct 2016 07:05:40 -0400
Date: Mon, 17 Oct 2016 13:03:01 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
        Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Stephane Eranian <eranian@google.com>, Borislav Petkov <bp@suse.de>,
        Dave Hansen <dave.hansen@intel.com>,
        Nilay Vaish <nilayvaish@gmail.com>, Shaohua Li <shli@fb.com>,
        David Carrillo-Cisneros <davidcc@google.com>,
        Ravi V Shankar <ravi.v.shankar@intel.com>,
        Sai Prakhya <sai.praneeth.prakhya@intel.com>,
        Vikas Shivappa <vikas.shivappa@linux.intel.com>,
        linux-kernel <linux-kernel@vger.kernel.org>, x86 <x86@kernel.org>
Subject: Re: [PATCH v4 07/18] x86/intel_rdt: Add Haswell feature discovery
In-Reply-To: <1476497548-11169-8-git-send-email-fenghua.yu@intel.com>
Message-ID: <alpine.DEB.2.20.1610171257451.4912@nanos>
References: <1476497548-11169-1-git-send-email-fenghua.yu@intel.com> <1476497548-11169-8-git-send-email-fenghua.yu@intel.com>
User-Agent: Alpine 2.20 (DEB 67 2015-01-07)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Fri, 14 Oct 2016, Fenghua Yu wrote:
> +static inline bool cache_alloc_hsw_probe(void)
> +{
> +	u32 l, h;
> +	u32 max_cbm = BIT_MASK(20) - 1;

Two options here:

+	u32 l, h, max_cbm = BIT_MASK(20) - 1;

or

+	u32 max_cbm = BIT_MASK(20) - 1;
+	u32 l, h;

I personally prefer #1, but I can accept #2 as well. Both are quick to
parse while the one you chose is stopping the reading flow.

> +
> +	if (wrmsr_safe(IA32_L3_CBM_BASE, max_cbm, 0))
> +		return false;
> +	rdmsr(IA32_L3_CBM_BASE, l, h);
> +	if (l != max_cbm)
> +		return false;
> +
> +	return true;

  	return l == max_cbm;

Hmm?

> +}
> +
>  static inline bool get_rdt_resources(void)
>  {
>  	bool ret = false;
>  
> +	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
> +	    boot_cpu_data.x86 == 6 &&
> +	    boot_cpu_data.x86_model == INTEL_FAM6_HASWELL_X)
> +		return cache_alloc_hsw_probe();

Can you please stick that model check into the probe function and do:

    	if (cache_alloc_hsw_probe())
		return true;
> +
>  	if (!boot_cpu_has(X86_FEATURE_RDT_A))
>  		return false;
>  	if (boot_cpu_has(X86_FEATURE_CAT_L3))

Thanks,

	tglx