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Date: Mon, 17 Oct 2016 18:53:31 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
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Subject: Re: [PATCH v4 08/18] x86/intel_rdt: Pick up L3/L2 RDT parameters
 from CPUID
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On Mon, 17 Oct 2016, Fenghua Yu wrote:
> On Mon, Oct 17, 2016 at 03:45:32PM +0200, Thomas Gleixner wrote:
> > On Fri, 14 Oct 2016, Fenghua Yu wrote:
> > > +/**
> > > + * struct rdt_resource - attributes of an RDT resource
> > > + * @enabled:			Is this feature enabled on this machine
> > > + * @name:			Name to use in "schemata" file
> > > + * @max_closid:			Maximum number of CLOSIDs supported
> > > + * @num_closid:			Current number of CLOSIDs available
> > > + * @max_cbm:			Largest Cache Bit Mask allowed
> > > + * @min_cbm_bits:		Minimum number of bits to be set in a cache
> > 
> > That should be 'number of consecutive bits', right?
> 
> Change to "Minimum number of consecutive bits to be set in a cache", is
> that ok?

Yes.
 
Thanks,

	tglx