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Date: Wed, 26 Oct 2016 16:28:45 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@suse.de>
cc: Fenghua Yu <fenghua.yu@intel.com>,
        "H. Peter Anvin" <h.peter.anvin@intel.com>,
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Subject: Re: [PATCH v5 04/18] x86/intel_rdt: Feature discovery
In-Reply-To: <20161026141502.zzfuwlnnoe2jfu6n@pd.tnic>
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References: <1477142405-32078-1-git-send-email-fenghua.yu@intel.com> <1477142405-32078-5-git-send-email-fenghua.yu@intel.com> <20161026141502.zzfuwlnnoe2jfu6n@pd.tnic>
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On Wed, 26 Oct 2016, Borislav Petkov wrote:
> > +#define X86_FEATURE_CAT_L3	( 7*32+16) /* Cache Allocation Technology L3 */
> > +#define X86_FEATURE_CAT_L2	( 7*32+17) /* Cache Allocation Technology L2 */
> > +#define X86_FEATURE_CDP_L3	( 7*32+18) /* Code and Data Prioritization L3 */
> 
> Also, this patch or even better, the whole patchset needs to be at least
> test-merged with tip/master to check for conflicting changes. Like this
> one here:
> 
> #define X86_FEATURE_INTEL_PT    ( 7*32+15) /* Intel Processor Trace */
> #define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network Instructions */
> #define X86_FEATURE_CAT_L3      ( 7*32+16) /* Cache Allocation Technology L3 */

That's an easy one to fixup and I prefer a clean patch against Linus tree
at the moment.

Thanks,

	tglx