From: Thomas Gleixner <tglx@linutronix.de>
To: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Cc: mingo@redhat.com, hpa@zytor.com, x86@kernel.org, bp@suse.de,
dave.hansen@linux.intel.com, lukasz.daniluk@intel.com,
james.h.cownie@intel.com, jacob.jun.pan@intel.com,
Piotr.Luc@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features
Date: Sun, 30 Oct 2016 19:15:06 -0600 (MDT) [thread overview]
Message-ID: <alpine.DEB.2.20.1610300914560.6965@nanos> (raw)
In-Reply-To: <1477662595-21011-4-git-send-email-grzegorz.andrejczuk@intel.com>
On Fri, 28 Oct 2016, Grzegorz Andrejczuk wrote:
> Add Intel Xeon Phi x200 (KnightsLanding) cpu feature - ring 3 monitor/mwait
>
> Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 92a8308..eb88eeb 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -101,6 +101,7 @@
> #define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
> #define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
> /* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
Bah. Do you really think that this comment is still useful? Can you please
get your act together and switch on your brain instead of mindlessly
slapping stuff into the code?
> +#define X86_FEATURE_PHIR3MWAIT ( 3*32+25) /* Xeon Phi x200 ring 3 MONITOR/MWAIT */
Thanks,
tglx
next prev parent reply other threads:[~2016-10-31 1:17 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-28 13:49 [PATCH v7 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-10-28 13:49 ` [PATCH v7 1/4] x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h Grzegorz Andrejczuk
2016-10-31 1:14 ` Thomas Gleixner
2016-10-28 13:49 ` [PATCH v7 2/4] x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT Grzegorz Andrejczuk
2016-10-31 1:14 ` Thomas Gleixner
2016-10-28 13:49 ` [PATCH v7 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
2016-10-31 1:15 ` Thomas Gleixner [this message]
2016-10-28 13:49 ` [PATCH v7 4/4] x86: Add enabling of the R3MWAIT during boot Grzegorz Andrejczuk
2016-10-31 1:15 ` Thomas Gleixner
2016-12-03 20:27 ` [PATCH v7 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Pavel Machek
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=alpine.DEB.2.20.1610300914560.6965@nanos \
--to=tglx@linutronix.de \
--cc=Piotr.Luc@intel.com \
--cc=bp@suse.de \
--cc=dave.hansen@linux.intel.com \
--cc=grzegorz.andrejczuk@intel.com \
--cc=hpa@zytor.com \
--cc=jacob.jun.pan@intel.com \
--cc=james.h.cownie@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=lukasz.daniluk@intel.com \
--cc=mingo@redhat.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®