From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933717AbcJaBSO (ORCPT ); Sun, 30 Oct 2016 21:18:14 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:51403 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933642AbcJaBSI (ORCPT ); Sun, 30 Oct 2016 21:18:08 -0400 Date: Sun, 30 Oct 2016 19:14:17 -0600 (MDT) From: Thomas Gleixner To: Grzegorz Andrejczuk cc: mingo@redhat.com, hpa@zytor.com, x86@kernel.org, bp@suse.de, dave.hansen@linux.intel.com, lukasz.daniluk@intel.com, james.h.cownie@intel.com, jacob.jun.pan@intel.com, Piotr.Luc@intel.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 1/4] x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h In-Reply-To: <1477662595-21011-2-git-send-email-grzegorz.andrejczuk@intel.com> Message-ID: References: <1477662595-21011-1-git-send-email-grzegorz.andrejczuk@intel.com> <1477662595-21011-2-git-send-email-grzegorz.andrejczuk@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 28 Oct 2016, Grzegorz Andrejczuk wrote: > Subject: x86/msr: Add MSR(140H) and PHIR3MWAIT bit to msr-info.h What kind of information is this: MSR(140h)? None at all. That MSR has a name. So why not using it? x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Hmm? You might have noticed that I removed the 'to msr-info.h' part. I did this because it's useless information. We can see that from the patch. > Intel Xeon Phi x200 (codenamed Knights Landing) has MSR > MISC_FEATURE_ENABLES 0x140. And that tells us what? > Setting 2nd bit of this register makes MONITOR and MWAIT instructions > do not cause invalid-opcode exception when called from ring different > than 0. Can you please be a bit more careful with your changelogs? I give you an example for a proper one: Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable MONITOR and MWAIT instructions outside of ring 0. The feature is controlled by MSR MISC_FEATURE_ENABLES (0x144). Setting bit 0 of this register enables it, so MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when invoked outside of ring 0. The feature MSR is not yet documented in the SDM. Here is the relevant documentation: Can you spot the difference? Hint: Copy and paste are dangerous > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -540,6 +540,11 @@ > #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 > #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) > > +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ > +#define MSR_MISC_FEATURE_ENABLES 0x00000140 > +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1 > +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT) > + See comment on patch 4/4 why this bit mask is not required. Thanks, tglx