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Date: Tue, 15 Nov 2016 17:40:05 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
To: Fenghua Yu <fenghua.yu@intel.com>
cc: "H. Peter Anvin" <h.peter.anvin@intel.com>,
        Ingo Molnar <mingo@elte.hu>, Tony Luck <tony.luck@intel.com>,
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        Vikas Shivappa <vikas.shivappa@linux.intel.com>,
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Subject: Re: [PATCH 3/3] x86/intel_rdt: Update closid in PQR_ASSOC registers
 in synchronous mode when changing "cpus"
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References: <1478912558-55514-1-git-send-email-fenghua.yu@intel.com> <1478912558-55514-3-git-send-email-fenghua.yu@intel.com> <alpine.DEB.2.20.1611151451330.3602@nanos>
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On Tue, 15 Nov 2016, Thomas Gleixner wrote:

> On Fri, 11 Nov 2016, Fenghua Yu wrote:
> > +/*
> > + * MSR_IA32_PQR_ASSOC is scoped per logical CPU, so all updates
> > + * are always in thread context.
> 
> And this comment tells us what? Nothing useful. It lacks the most important
> information why this is safe against a logical CPU switching the MSR right
> at this moment during context switch. It's safe because the pqr_switch_to
> function is called with interrupts disabled.
> 
> > + */
> > +static void rdt_update_pqr_assoc_closid(void *v)
> > +{
> > +	struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
> > +
> > +	state->closid = *(int *)v;
> > +	wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, state->closid);

Furthermore, unconditionally writting the MSR is Just Wrong because the
current executing task might have it's own closid set which gets
overwritten by this.

No cookies!

	tglx