From: Thomas Gleixner <tglx@linutronix.de>
To: Andy Lutomirski <luto@amacapital.net>
Cc: LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Kyle Huey <khuey@kylehuey.com>, Andy Lutomirski <luto@kernel.org>
Subject: Re: [patch 3/3] x86/process: Optimize TIF_NOTSC switch
Date: Fri, 16 Dec 2016 09:50:04 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.20.1612160947410.3470@nanos> (raw)
In-Reply-To: <CALCETrUbzDAfjnLqsFpAdOkx9qK0ircasXXqUzQ4ON-oq31fRg@mail.gmail.com>
On Thu, 15 Dec 2016, Andy Lutomirski wrote:
> On Thu, Dec 15, 2016 at 8:44 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> > +static inline void cr4_toggle_bits(unsigned long mask)
> > +{
> > + unsigned long cr4;
> > +
> > + cr4 = this_cpu_read(cpu_tlbstate.cr4);
> > + cr4 ^= mask;
> > + this_cpu_write(cpu_tlbstate.cr4, cr4);
> > + __write_cr4(cr4);
> > +}
>
> This scares me for the same reason as BTF, although this should at
> least be less fragile. But how about:
If that is fragile then all cr4 manipulation code is fragile because it
relies on cpu_tlbstate.cr4. The TIF flag and that per cpu thing are kept in
sync.
Thanks,
tglx
next prev parent reply other threads:[~2016-12-16 8:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-15 16:44 [patch 0/3] x86/process: Optimize __switch_to_extra() Thomas Gleixner
2016-12-15 16:44 ` [patch 2/3] x86/process: Optimize TIF_BLOCKSTEP switch Thomas Gleixner
2016-12-15 17:28 ` Andy Lutomirski
2016-12-16 8:47 ` Thomas Gleixner
2016-12-16 19:22 ` Andy Lutomirski
2016-12-15 16:44 ` [patch 1/3] x86/process: Optimize TIF checks in switch_to_extra() Thomas Gleixner
2016-12-15 17:20 ` Peter Zijlstra
2016-12-15 17:26 ` Thomas Gleixner
2016-12-15 17:33 ` Peter Zijlstra
2016-12-15 17:24 ` Andy Lutomirski
2016-12-15 16:44 ` [patch 3/3] x86/process: Optimize TIF_NOTSC switch Thomas Gleixner
2016-12-15 17:31 ` Andy Lutomirski
2016-12-16 8:50 ` Thomas Gleixner [this message]
2016-12-16 18:34 ` Andy Lutomirski
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