From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: x86@kernel.org, Peter Zijlstra <peterz@infradead.org>,
Borislav Petkov <bp@alien8.de>,
Bruce Schlobohm <bruce.schlobohm@intel.com>,
Roland Scheidegger <rscheidegger_lists@hispeed.ch>,
Kevin Stanton <kevin.b.stanton@intel.com>,
Allen Hung <allen_hung@dell.com>,
stable@vger.kernel.org
Subject: Re: [patch 2/2] x86/tsc: Force TSC_ADJUST register to value >= zero
Date: Fri, 16 Dec 2016 12:46:12 +0100 (CET) [thread overview]
Message-ID: <alpine.DEB.2.20.1612161121140.3470@nanos> (raw)
In-Reply-To: <20161213131211.397588033@linutronix.de>
On Tue, 13 Dec 2016, Thomas Gleixner wrote:
> Roland reported that his DELL T5810 sports a value add BIOS which
> completely wreckages the TSC. The squirmware [(TM) Ingo Molnar] boots with
> random negative TSC_ADJUST values, different on all CPUs. That renders the
> TSC useless because the sycnchronization check fails.
While everyone assumed that this is the usual DELL squirmware problem, I
have to say it's not.
Just got my hands on a Skylake based Lenovo S510 box and it shows the same
feature:
TSC ADJUST: CPU0: -10123656703215
CPU1: -10123656796701
CPU2: -10123656797460
CPU3: -10123656798366
Which causes the TSC to be out of sync on a stock upstream kernel and the
TSC deadline timer wreckage is happening on that machine as well.
I'm pretty sure, that this well thought out feature to 'hide power on time'
from TSC has not been independently 'invented' by DELL and Lenovo BIOS
tinkerers.
I rather have the impression that this is an advisory or feature kit from
some other entity. Whoever came up with this misfeature at Intel and/or
Microsoft (sorry, I could not come up with any other suspects) should be
promoted to run the 'Linux on feature-plagued systems' hot line.
As this seems to be more wide spread than we thought initially, we have to
think about a solution for stable kernels, especially 4.9. And distros will
have to think about that as well....
We have two options:
1) Disable TSC deadline timer by default and force users with sane machines
to enable it on the kernel command line.
Upside: Very small patch
Downside: Degrades existing setups on sane machines, keeps TSC unusable
on affected machines. We have no idea what other hidden side
effects the TSC_ADJUST tinkering has. If there are any, they
ain't be nice ones.
2) Push the whole TSC_ADJUST sanitizing machinery into stable
Upside: Does not affect sane machines and gives a benefit to users of
affected machines
Downside: Rather large patch, but not that risky either. Needs a few
eyes and good test coverage though
Thoughts?
tglx
next prev parent reply other threads:[~2016-12-16 11:49 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 13:14 [patch 0/2] tsc/adjust: Cure suspend/resume issues and prevent TSC deadline timer irq storm Thomas Gleixner
2016-12-13 13:14 ` [patch 1/2] x86/tsc: Validate TSC_ADJUST after resume Thomas Gleixner
2016-12-13 13:22 ` Peter Zijlstra
2016-12-13 13:23 ` Thomas Gleixner
2016-12-15 10:52 ` [tip:x86/timers] " tip-bot for Thomas Gleixner
2016-12-13 13:14 ` [patch 2/2] x86/tsc: Force TSC_ADJUST register to value >= zero Thomas Gleixner
2016-12-13 13:43 ` Peter Zijlstra
2016-12-13 15:49 ` Thomas Gleixner
2016-12-15 10:53 ` [tip:x86/timers] " tip-bot for Thomas Gleixner
2016-12-16 11:46 ` Thomas Gleixner [this message]
2016-12-16 11:52 ` [patch 2/2] " Ingo Molnar
2016-12-16 11:53 ` Thomas Gleixner
2016-12-16 13:33 ` Thomas Gleixner
2016-12-13 16:34 ` [patch 0/2] tsc/adjust: Cure suspend/resume issues and prevent TSC deadline timer irq storm Roland Scheidegger
2016-12-13 16:46 ` Thomas Gleixner
2016-12-14 1:36 ` Roland Scheidegger
2016-12-14 7:31 ` Thomas Gleixner
2016-12-14 20:59 ` Thomas Gleixner
2016-12-14 21:40 ` Thomas Gleixner
2016-12-14 22:54 ` Roland Scheidegger
2016-12-15 9:31 ` Thomas Gleixner
2017-01-26 23:40 ` Stanton, Kevin B
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