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From: Thomas Gleixner <tglx@linutronix.de>
To: Kan Liang <kan.liang@intel.com>
Cc: peterz@infradead.org, mingo@redhat.com,
	linux-kernel@vger.kernel.org, bp@alien8.de, acme@kernel.org,
	eranian@google.com, jolsa@kernel.org, ak@linux.intel.com
Subject: Re: [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI
Date: Tue, 28 Mar 2017 10:42:13 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1703281036520.3616@nanos> (raw)
In-Reply-To: <1490639448-4147-3-git-send-email-kan.liang@intel.com>

On Mon, 27 Mar 2017, kan.liang@intel.com wrote:
> +
> +	if (val)
> +		msr_set_bit_on_cpus(cpu_possible_mask, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
> +	else
> +		msr_clear_bit_on_cpus(cpu_possible_mask, MSR_IA32_DEBUGCTLMSR, DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);

This is still not protected against CPU hotplug. What's so hard about:

	get_online_cpus();

	if (val) {
		msr_set_bit_on_cpus(cpu_online_mask, MSR_IA32_DEBUGCTLMSR,
				    DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
	} else {
		msr_clear_bit_on_cpus(cpu_online_mask, MSR_IA32_DEBUGCTLMSR,
				      DEBUGCTLMSR_FREEZE_WHILE_SMM_BIT);
	}

	put_online_cpus();

Aside of that, when this is set to SMI freeze, what causes a CPU which
comes online after that point to set the bit as well? Nothing AFAICT.

Thanks,

	tglx

  reply	other threads:[~2017-03-28  8:42 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-27 18:30 [PATCH V3 0/2] measure SMI cost (kernel) kan.liang
2017-03-27 18:30 ` [PATCH V3 1/2] x86/msr: add msr_set/clear_bit_on_cpu/cpus access functions kan.liang
2017-03-28  8:36   ` Thomas Gleixner
2017-03-28 17:23     ` Thomas Gleixner
2017-03-28 17:38       ` Liang, Kan
2017-03-28 18:34         ` Thomas Gleixner
2017-03-27 18:30 ` [PATCH V3 2/2] perf/x86: add sysfs entry to freeze counter on SMI kan.liang
2017-03-28  8:42   ` Thomas Gleixner [this message]
2017-03-28 13:23     ` Liang, Kan
2017-03-28 17:03       ` Thomas Gleixner

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