From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932945AbdKBNrL (ORCPT ); Thu, 2 Nov 2017 09:47:11 -0400 Received: from Galois.linutronix.de ([146.0.238.70]:54367 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932176AbdKBNrK (ORCPT ); Thu, 2 Nov 2017 09:47:10 -0400 Date: Thu, 2 Nov 2017 14:46:59 +0100 (CET) From: Thomas Gleixner To: Kan Liang cc: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org, acme@kernel.org, eranian@google.com, ak@linux.intel.com Subject: Re: [PATCH V3 1/5] perf/x86/intel/uncore: customized pmu event read for client IMC uncore In-Reply-To: <1508843124-4081-1-git-send-email-kan.liang@intel.com> Message-ID: References: <1508843124-4081-1-git-send-email-kan.liang@intel.com> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 24 Oct 2017, kan.liang@intel.com wrote: > - if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) > + if (event->hw.idx == UNCORE_PMC_IDX_FIXED) > shift = 64 - uncore_fixed_ctr_bits(box); > else > shift = 64 - uncore_perf_ctr_bits(box); > diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c > index db1127c..9d5cd3f 100644 > --- a/arch/x86/events/intel/uncore_snb.c > +++ b/arch/x86/events/intel/uncore_snb.c > @@ -498,6 +498,30 @@ static void snb_uncore_imc_event_del(struct perf_event *event, int flags) > snb_uncore_imc_event_stop(event, PERF_EF_UPDATE); > } > > +static void snb_uncore_imc_event_read(struct perf_event *event) > +{ > + struct intel_uncore_box *box = uncore_event_to_box(event); > + u64 prev_count, new_count, delta; > + int shift; > + > + if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) And this needs to be >= because? > + shift = 64 - uncore_fixed_ctr_bits(box); > + else > + shift = 64 - uncore_perf_ctr_bits(box); Thanks, tglx