From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AH8x224HFvdUuNttdYkYpeLfctqDp6wmRo3ERnMNtUodOlZrRKDbyNC9XEndyp99Vvq2Z+6Xbd+F ARC-Seal: i=1; a=rsa-sha256; t=1516478903; cv=none; d=google.com; s=arc-20160816; b=KtCpFVAzuhrahmR6NtmIc5Q9WnBYId31BaUzFqTFGx60dUeWYxSo+/ZRoK6MaFnxLm Kj/eGfGMwtVtRx0HwQlAbAbBDLUw4NOlfqUQdFt9eRHpPEF4osjtCUeBOCqHuHsF3jXS B1lWvuxAu7kqFzuMFLIC94ZK6D11MoE3apiWx6um//FSlBilGNXW6pxodidU0VewErfw zkCAOiI1cz2LwkBP67eqcd411eQYKkw/qF42mh2JkNdB6ybYEhkNSeYLw8zmtgW8+MIY bD66WexXVpgHy3mtA/z4wRwH6EX9MWIrjOHabtPUfIZXDPCGt2u3CSRBZJNmhSvCBXNl EuqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:user-agent:references:message-id:in-reply-to:subject :cc:to:from:date:arc-authentication-results; bh=NTyvqzK6wS56aTrsgNiTCLVNCx8U9SUmeI/ZDt3yRcc=; b=GF9Iaj99VMf9/UcEStP6BF2cHgHpBaMfXMd8I36UYaFrZ00ULPUFWWYtsbtyP9FWiQ 6ogatFM5W69SxaP7YMlrlDEGdJ4BGc3mqz+bEzqB5jEyeT4Ya5lw77WMpE7jGbhuOU9y 7Kx3L7734ECVsffdXm3V+6U7oX1QZIXuH7bWE8CTWldR40fCVFhiDtFU3SrX0iKcxcga UcsYTOQv4lkJOa+56x1duALSYqUHXEVBFF0bSK8V6Upt3MYoezKXgq5MBhiaC8LUT7o8 D7JXcnHwO/VfCVlD8hvo0WDxbja3r0ZODIZNwBONly/M8FnmneZ6UXS9vfXstesrvveG xJ5A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a01:7a0:2:106d:700::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a01:7a0:2:106d:700::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de Date: Sat, 20 Jan 2018 21:08:11 +0100 (CET) From: Thomas Gleixner To: David Woodhouse cc: arjan@linux.intel.com, karahmed@amazon.de, x86@kernel.org, linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de, peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com, torvalds@linux-foundation.org, gregkh@linux-foundation.org Subject: Re: [PATCH 4/4] x86/pti: Do not enable PTI on fixed Intel processors In-Reply-To: <1516449813-7654-5-git-send-email-dwmw@amazon.co.uk> Message-ID: References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> <1516449813-7654-5-git-send-email-dwmw@amazon.co.uk> User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590113012988085522?= X-GMAIL-MSGID: =?utf-8?q?1590143383396266128?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Sat, 20 Jan 2018, David Woodhouse wrote: > When they advertise the IA32_ARCH_CAPABILITIES MSR and it has the RDCL_NO > bit set, they don't need KPTI either. Do they exist today? And do we have documentation for that new MSR already? Thanks, tglx > Signed-off-by: David Woodhouse > --- > arch/x86/kernel/cpu/common.c | 9 +++++++-- > 1 file changed, 7 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > index e5d66e9..80572ae 100644 > --- a/arch/x86/kernel/cpu/common.c > +++ b/arch/x86/kernel/cpu/common.c > @@ -900,8 +900,13 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) > > setup_force_cpu_cap(X86_FEATURE_ALWAYS); > > - if (c->x86_vendor != X86_VENDOR_AMD) > - setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); > + if (c->x86_vendor != X86_VENDOR_AMD) { > + unsigned long ia32_cap = 0; > + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) > + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); > + if (!(ia32_cap & ARCH_CAP_RDCL_NO)) > + setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN); > + } > > setup_force_cpu_bug(X86_BUG_SPECTRE_V1); > setup_force_cpu_bug(X86_BUG_SPECTRE_V2); > -- > 2.7.4 > >