From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <tglx@linutronix.de>
X-Google-Smtp-Source: AH8x227x9Do+2xD1x3t4c5m1O8zldBuUqTDdPWL83GjumVkmK/yZvSgK97R4RUX0/VmLBfco14T5
ARC-Seal: i=1; a=rsa-sha256; t=1516479196; cv=none;
        d=google.com; s=arc-20160816;
        b=Sqp0Brn+Gdp4M9C9+rZUOo3kM2dKrAZ5xP0KJxIVdVUDbOfz4wXoqbq5lLv6vEMwwK
         bzZ3YiOlbk/FnyfXDhtzaMK0dtk79NyQwHU23B5/ISerULyMSsTqcJDAROSB0sM/OpS3
         rVrW2FNZnDYNw5+6M3bLUjR5zWYTr+qekPdvXR2ZUnnNXPEvgWSeoN7F1xYrldwJJlVx
         eM37lcLIEw+D6bBYStAGAfmZO6LEnFMtdD25Y3oOmHa8KsUM6wPj6Gyuf6RzZyCwAecG
         Sk4k9U+jCu1IPa0SHAHLT79r2q5iypoBIiAin8nIQ9edrMzJsimJP3WCPmwWxQDBFIg/
         gaDg==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=mime-version:user-agent:references:message-id:in-reply-to:subject
         :cc:to:from:date:arc-authentication-results;
        bh=6GQtepeKPBDRLgSbjd65H+KrGlvw50BsIt+xQ1ma/OA=;
        b=TW9HEHbUppGKshWpBHFs1rgu+UgO+mSVU01dqmElREKIqgsfNFGwXEDX1jyTfNy7wk
         j060lyORVwuCYRftUjql2xLbCu9bRGGab8AdVzPnCdUYkXDXngI3PXCLekNQZbRaIfuv
         tAdcnI/5KYqYQora4OJfkUbQLmH4ev6R99CLG3D/NMbjowJ7TriQ2OfMLnLTkUVcKXTJ
         yfR431Azn2sRNiKUfFBWmd0cRc8BEItCOWN/+JnXAPbikp+uCembMmXRzuJ6Vg6lbcQU
         5iy8j5cUeAqDbv/r/gQyASU2B034/oTrT2gEPtPBORfv9Crl2iFJWB3A6TMFsx5JKlbt
         BiWw==
ARC-Authentication-Results: i=1; mx.google.com;
       spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a01:7a0:2:106d:700::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de
Authentication-Results: mx.google.com;
       spf=pass (google.com: best guess record for domain of tglx@linutronix.de designates 2a01:7a0:2:106d:700::1 as permitted sender) smtp.mailfrom=tglx@linutronix.de
Date: Sat, 20 Jan 2018 21:13:05 +0100 (CET)
From: Thomas Gleixner <tglx@linutronix.de>
To: David Woodhouse <dwmw@amazon.co.uk>
cc: arjan@linux.intel.com, karahmed@amazon.de, x86@kernel.org,
    linux-kernel@vger.kernel.org, tim.c.chen@linux.intel.com, bp@alien8.de,
    peterz@infradead.org, pbonzini@redhat.com, ak@linux.intel.com,
    torvalds@linux-foundation.org, gregkh@linux-foundation.org
Subject: Re: [PATCH 4/4] x86/pti: Do not enable PTI on fixed Intel
 processors
In-Reply-To: <alpine.DEB.2.20.1801202107300.1998@nanos>
Message-ID: <alpine.DEB.2.20.1801202111560.1998@nanos>
References: <1516449813-7654-1-git-send-email-dwmw@amazon.co.uk> <1516449813-7654-5-git-send-email-dwmw@amazon.co.uk> <alpine.DEB.2.20.1801202107300.1998@nanos>
User-Agent: Alpine 2.20 (DEB 67 2015-01-07)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
X-Linutronix-Spam-Score: -1.0
X-Linutronix-Spam-Level: -
X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required,  ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001
X-getmail-retrieved-from-mailbox: INBOX
X-GMAIL-THRID: =?utf-8?q?1590113012988085522?=
X-GMAIL-MSGID: =?utf-8?q?1590143689690363043?=
X-Mailing-List: linux-kernel@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>



On Sat, 20 Jan 2018, Thomas Gleixner wrote:

> On Sat, 20 Jan 2018, David Woodhouse wrote:
> 
> > When they advertise the IA32_ARCH_CAPABILITIES MSR and it has the RDCL_NO
> > bit set, they don't need KPTI either.
> 
> Do they exist today? And do we have documentation for that new MSR already?

Scratch the seconds question. It's in that spec mitigations PDF.

The first question stands.

Thanks,

	tglx