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From: Thomas Gleixner <tglx@linutronix.de>
To: Alan Cox <gnomes@lxorguk.ukuu.org.uk>
Cc: "Gustavo A. R. Silva" <garsilva@embeddedor.com>,
	Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@redhat.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/microcode/intel: Use 64-bit arithmetic instead of 32-bit
Date: Wed, 14 Feb 2018 12:39:09 +0100 (CET)	[thread overview]
Message-ID: <alpine.DEB.2.21.1802141235570.1292@nanos.tec.linutronix.de> (raw)
In-Reply-To: <20180213231847.36f87c0b@alans-desktop>

On Tue, 13 Feb 2018, Alan Cox wrote:
> > 	if (c->x86_cache_size >= 0)
> > 		seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
> > 
> > which is silly, because that really can be done with:
> > 
> > 	if (c->x86_cache_size)
> > 
> > as there is no point in printing 'cache size 0KB', which means
> > x86_cache_size can be made unsigned int, which makes sense because cache
> > size < 0 does not at all.
> 
> Currently 0MB means "I know you have no cache" (early slot 1 celeron),
> while not printing it means 'I have no clue'

Cute. I hope the 3 slot1 celeron users will not go wild if their
/proc/cpuinfo now claims to have no clue about caches.

Thanks,

	tglx

      reply	other threads:[~2018-02-14 11:39 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-13 16:44 Gustavo A. R. Silva
2018-02-13 17:02 ` Thomas Gleixner
2018-02-13 17:24   ` Gustavo A. R. Silva
2018-02-13 23:18   ` Alan Cox
2018-02-14 11:39     ` Thomas Gleixner [this message]

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