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[67.0.62.24]) by smtp.gmail.com with ESMTPSA id c81sm13381678iof.28.2019.07.12.10.16.41 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Fri, 12 Jul 2019 10:16:41 -0700 (PDT) Date: Fri, 12 Jul 2019 10:16:40 -0700 (PDT) From: Paul Walmsley X-X-Sender: paulw@viisi.sifive.com To: Atish Patra cc: linux-kernel@vger.kernel.org, Jeremy Linton , Albert Ou , Anup Patel , Catalin Marinas , "David S. Miller" , devicetree@vger.kernel.org, Greg Kroah-Hartman , Ingo Molnar , Johan Hovold , Linus Walleij , linux-riscv@lists.infradead.org, Mark Rutland , Mauro Carvalho Chehab , Morten Rasmussen , Otto Sabart , Palmer Dabbelt , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Sudeep Holla , Thomas Gleixner , Will Deacon , Will Deacon , linux-arm-kernel@lists.infradead.org, Russell King Subject: Re: [PATCH v8 0/7] Unify CPU topology across ARM & RISC-V In-Reply-To: <20190627195302.28300-1-atish.patra@wdc.com> Message-ID: References: <20190627195302.28300-1-atish.patra@wdc.com> User-Agent: Alpine 2.21.9999 (DEB 301 2018-08-15) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Folks, On Thu, 27 Jun 2019, Atish Patra wrote: > The cpu-map DT entry in ARM can describe the CPU topology in much better > way compared to other existing approaches. RISC-V can easily adopt this > binding to represent its own CPU topology. Thus, both cpu-map DT > binding and topology parsing code can be moved to a common location so > that RISC-V or any other architecture can leverage that. > > The relevant discussion regarding unifying cpu topology can be found in > [1]. > > arch_topology seems to be a perfect place to move the common code. I > have not introduced any significant functional changes in the moved code. > The only downside in this approach is that the capacity code will be > executed for RISC-V as well. But, it will exit immediately after not > able to find the appropriate DT node. If the overhead is considered too > much, we can always compile out capacity related functions under a > different config for the architectures that do not support them. > > There was an opportunity to unify topology data structure for ARM32 done > by patch 3/4. But, I refrained from making any other changes as I am not > very well versed with original intention for some functions that > are present in arch_topology.c. I hope this patch series can be served > as a baseline for such changes in the future. > > The patches have been tested for RISC-V, ARM64, ARM32 & compile tested for > x86. Since these patches touch files across several different architectures, and thus really should sit in -next for a while; and because it's late in the merge window, I'm planning to postpone sending these patches upstream until after v5.3-rc1 is released. Once v5.3-rc1 is released, let's plan to get these patches rebased and reposted and into linux-next as soon as possible. Sorry for the delay here, - Paul