From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner+w=401wt.eu-S1755480AbYFRV6j@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1755480AbYFRV6j (ORCPT <rfc822;w@1wt.eu>);
	Wed, 18 Jun 2008 17:58:39 -0400
Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1754062AbYFRV6b
	(ORCPT <rfc822;linux-kernel-outgoing>);
	Wed, 18 Jun 2008 17:58:31 -0400
Received: from www.tglx.de ([62.245.132.106]:46496 "EHLO www.tglx.de"
	rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP
	id S1754090AbYFRV6a (ORCPT <rfc822;linux-kernel@vger.kernel.org>);
	Wed, 18 Jun 2008 17:58:30 -0400
Date: Wed, 18 Jun 2008 23:58:06 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: "Rafael J. Wysocki" <rjw@sisk.pl>
cc: Pavel Machek <pavel@suse.cz>, LKML <linux-kernel@vger.kernel.org>,
       Ingo Molnar <mingo@elte.hu>, Arjan van de Veen <arjan@infradead.org>,
       Andreas Herrmann <andreas.herrmann3@amd.com>
Subject: Re: [patch 6/6] x86: add c1e aware idle function
In-Reply-To: <200806182226.07590.rjw@sisk.pl>
Message-ID: <alpine.LFD.1.10.0806182354280.3395@apollo.tec.linutronix.de>
References: <20080610171639.551369443@linutronix.de> <20080610171712.465591661@linutronix.de> <20080618192148.GA4243@ucw.cz> <200806182226.07590.rjw@sisk.pl>
User-Agent: Alpine 1.10 (LFD 962 2008-03-14)
MIME-Version: 1.0
Content-Type: TEXT/PLAIN; charset=US-ASCII
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Wed, 18 Jun 2008, Rafael J. Wysocki wrote:
> On Wednesday, 18 of June 2008, Pavel Machek wrote:
> > On Thu 2008-06-12 10:29:00, Thomas Gleixner wrote:
> > > C1E on AMD machines is like C3 but without control from the OS. Up to
> > > now we disabled the local apic timer for those machines as it stops
> > > when the CPU goes into C1E. This excludes those machines from high
> > > resolution timers / dynamic ticks, which hurts especially the X2 based
> > > laptops.
> > > 
> > > The current boot time C1E detection has another more serious flaw:
> > > some BIOSes do not enable C1E until the ACPI processor module is
> > > loaded. This causes systems to stop working after that point.
> > > 
> > > To work nicely with C1E enabled machines we use a separate idle
> > > function, which checks on idle entry whether C1E was enabled in the
> > > Interrupt Pending Message MSR. This allows us to do timer broadcasting
> > 
> > Entering idle is quite a common operation, and reading MSR is quite
> > slow. Is it possible to do better here?
> > 
> > What happens if ACPI BIOS toggles MSR on all cpus *while* we are
> > entering idle? This seems inherently racy...

Well, on most of the machines we see the C1E bit on the first idle
entry either on CPU0 or on CPU1.

I know of exactly one machine which has the C1E thing enabled late
when the ACPI stuff runs.
 
> Yes, and that fits the picture I'm observing on the nx6325 (see the
> "linux-next: Tree for June 13: IO APIC breakage on HP nx6325" thread).

Hmm, when is the C1E detected on current mainline ? Does the boot CPU
have it or is it when the second CPU comes up ?

Thanks,
	tglx