From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754247AbZENT1e (ORCPT ); Thu, 14 May 2009 15:27:34 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751766AbZENT1Z (ORCPT ); Thu, 14 May 2009 15:27:25 -0400 Received: from www.tglx.de ([62.245.132.106]:45788 "EHLO www.tglx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751861AbZENT1Y (ORCPT ); Thu, 14 May 2009 15:27:24 -0400 Date: Thu, 14 May 2009 21:26:51 +0200 (CEST) From: Thomas Gleixner To: Dimitri Sivanich cc: LKML , Andrew Morton , Peter Zijlstra , Ingo Molnar Subject: Re: [patch 0/2] sched, timers: simplify calc_load and avoid cpu iteration loop In-Reply-To: <20090514172328.GA25691@sgi.com> Message-ID: References: <20090514105915.973318588@linutronix.de> <20090514172328.GA25691@sgi.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 14 May 2009, Dimitri Sivanich wrote: > I ran this patchset on a 64p ia64 machine and latency-wise it looks good. I can't really speak for the loadavg calculation. I did some comparisons vs. the old implementation and it looks pretty much the same. Thanks for testing, tglx