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Date: Fri, 29 Oct 2010 14:14:12 +0200 (CEST)
From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@amd64.org>
cc: Markus Trippelsdorf <markus@trippelsdorf.de>,
        Borislav Petkov <bp@alien8.de>, john stultz <johnstul@us.ibm.com>,
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Subject: Re: [bisected] Clocksource tsc unstable git
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On Fri, 29 Oct 2010, Borislav Petkov wrote:
> On Fri, Oct 29, 2010 at 04:30:13AM -0400, Markus Trippelsdorf wrote:
> That's strange, when we tested this one everything seemed fine so I
> guess this is one of those bugs which appear later, just as if out of
> nowhere.
> 
> Thomas, could it be that SMI fires in between the HPET write and
> subsequent read:
> 
> 	hpet_writel(cnt, HPET_Tn_CMP(timer));
> 
> 	...
> 
> 	res = (s32)(cnt - hpet_readl(HPET_COUNTER));
> 
> causing the -ETIME and thus a wait for HPET wraparound? My machine at
> least does SMI-initiated C1E so it could very well be the problem.

Well, even if a SMI fires, then the counter will be ahead of cnt and
we get -ETIME. The upper layer of clockevents/timers will then
reprogram HPET. So that's not an issue.

The only problem which might hit us is when our assumption of 8 HPET
cycles being enough to transfer the new match value into the real
match register is wrong.

Thanks,

	tglx