From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754345Ab1HJSWW (ORCPT ); Wed, 10 Aug 2011 14:22:22 -0400 Received: from vms173003pub.verizon.net ([206.46.173.3]:41244 "EHLO vms173003pub.verizon.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752502Ab1HJSWV (ORCPT ); Wed, 10 Aug 2011 14:22:21 -0400 Date: Wed, 10 Aug 2011 14:21:34 -0400 (EDT) From: Len Brown X-X-Sender: lenb@x980 To: Andrew Lutomirski Cc: Alan Cox , x86@kernel.org, linux-kernel@vger.kernel.org, Fenghua Yu , Matthew Garrett , linux-acpi@vger.kernel.org, Ingo Molnar Subject: Re: [PATCH v3 0/2] Forcibly enable some MISC_ENABLE features on Intel In-reply-to: Message-id: References: <20110809135050.79eed316@lxorguk.ukuu.org.uk> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) MIME-version: 1.0 Content-type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Andrew, FWIW, Intel's internal bug database claims this issue on your board is fixed in the next BIOS update. thanks, Len Brown, Intel Open Source Technology Center