From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756742Ab1KJWZA (ORCPT ); Thu, 10 Nov 2011 17:25:00 -0500 Received: from relais.videotron.ca ([24.201.245.36]:8785 "EHLO relais.videotron.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752218Ab1KJWY7 (ORCPT ); Thu, 10 Nov 2011 17:24:59 -0500 MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: TEXT/PLAIN; CHARSET=US-ASCII Date: Thu, 10 Nov 2011 17:24:58 -0500 (EST) From: Nicolas Pitre To: Catalin Marinas Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v8 09/16] ARM: LPAE: MMU setup for the 3-level page table format In-reply-to: <1320682618-1182-10-git-send-email-catalin.marinas@arm.com> Message-id: References: <1320682618-1182-1-git-send-email-catalin.marinas@arm.com> <1320682618-1182-10-git-send-email-catalin.marinas@arm.com> User-Agent: Alpine 2.02 (LFD 1266 2009-07-14) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 7 Nov 2011, Catalin Marinas wrote: [...] > + /* > + * Macro for setting up the TTBRx and TTBCR registers. > + * - \ttbr1 updated. > + */ > + .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp > + mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register > + orr \tmp, \tmp, #TTB_EAE > + ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) > + ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) > + ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) > + ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16) The ALT_SMP() and ALT_UP() must always be paired and in the right order. The above certainly won't produce what you expect on UP. > +#if PHYS_OFFSET <= PAGE_OFFSET Please don't use PHYS_OFFSET like a preprocessor macro anymore. This is becoming a global variable these days, and already is for the majority of platforms. > + * TTBR0/TTBR1 split (PAGE_OFFSET): > + * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) > + * 0x80000000: T0SZ = 0, T1SZ = 1 > + * 0xc0000000: T0SZ = 0, T1SZ = 2 > + * > + * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise > + * booting secondary CPUs would end up using TTBR1 for the identity > + * mapping set up in TTBR0. > + */ > + orr \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ > +#if defined CONFIG_VMSPLIT_2G > + /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */ > + add \ttbr1, \ttbr1, #1 << 4 @ skip two L1 entries > +#elif defined CONFIG_VMSPLIT_3G > + /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */ > + add \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd > +#endif > +#endif /* PHYS_OFFSET <= PAGE_OFFSET */ What about CONFIG_VMSPLIT_1G ? Nicolas