From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
	id S1752149AbbIGTaa (ORCPT <rfc822;w@1wt.eu>);
	Mon, 7 Sep 2015 15:30:30 -0400
Received: from eddie.linux-mips.org ([148.251.95.138]:38118 "EHLO
	cvs.linux-mips.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
	with ESMTP id S1751885AbbIGTa2 (ORCPT
	<rfc822;linux-kernel@vger.kernel.org>);
	Mon, 7 Sep 2015 15:30:28 -0400
Date: Mon, 7 Sep 2015 20:30:26 +0100 (BST)
From: "Maciej W. Rozycki" <macro@linux-mips.org>
To: Andy Lutomirski <luto@amacapital.net>
cc: Paolo Bonzini <pbonzini@redhat.com>, Ingo Molnar <mingo@kernel.org>,
        Borislav Petkov <bp@alien8.de>, Peter Zijlstra <peterz@infradead.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Willy Tarreau <w@1wt.eu>, Steven Rostedt <rostedt@goodmis.org>,
        X86 ML <x86@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>, Brian Gerst <brgerst@gmail.com>
Subject: Re: Dealing with the NMI mess
In-Reply-To: <CALCETrUf-EWOAZkAOm_mBWDMhTU4n=qtgm18Zhqhuv1jeg1f0g@mail.gmail.com>
Message-ID: <alpine.LFD.2.20.1509072012220.10227@eddie.linux-mips.org>
References: <20150724195509.GM2859@worktop.programming.kicks-ass.net> <CA+55aFzzrLY-0D+dK=EyKA+kZTiqzpEwFhJURbR76-7EuLhojA@mail.gmail.com> <20150724205119.GM19282@twins.programming.kicks-ass.net> <CALCETrX3L8W666xO15dU+mygFrk6mKJSEWCZ5K_A5SLBxAPZ0Q@mail.gmail.com>
 <55BA45A2.8050909@redhat.com> <CALCETrXDORrTifXjkf06QyhEDUumR8NBiAq5Tw_JLTt=iCB=Xw@mail.gmail.com> <20150731042205.GB32117@nazgul.tnic> <CALCETrX4wrVhXToC9oqo3Ma+smKf_8bhHD-D2FGxj3iGZ=ag6g@mail.gmail.com> <20150731080303.GA2128@nazgul.tnic>
 <alpine.LFD.2.20.1509070538540.10227@eddie.linux-mips.org> <20150907074218.GC19280@gmail.com> <alpine.LFD.2.20.1509070901390.10227@eddie.linux-mips.org> <55ED64C1.9090607@redhat.com> <alpine.LFD.2.20.1509071716030.10227@eddie.linux-mips.org>
 <CALCETrUf-EWOAZkAOm_mBWDMhTU4n=qtgm18Zhqhuv1jeg1f0g@mail.gmail.com>
User-Agent: Alpine 2.20 (LFD 67 2015-01-07)
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Sender: linux-kernel-owner@vger.kernel.org
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On Mon, 7 Sep 2015, Andy Lutomirski wrote:

> >  These are all implementation-specific details, including the INT1
> > instruction, which is why I am not at all surprised that they are omitted
> > from architecture manuals.
> 
> That bit is BS, though.  The INT1 instruction, executed in user mode
> (CPL3) with no hardware debugger attached, will enter the kernel
> through a gate at vector 1, *even if that gate has DPL == 0*.
> 
> If there's an instruction that bypasses hardware protection
> mechanisms, then Intel should document it rather than relying on OS
> writers to know enough folklore to get it right.
> 
> Heck, SDM Volume 3 6.12.1.1 says "The processor checks the DPL of the
> interrupt or trap gate only if an exception or interrupt is generated
> with an INT n, INT 3, or INTO instruction."  It does not say "the
> processor does not check the DPL of the interrupt or trap gate if the
> exception or interrupt is generated with the undocumented ICEBP
> instruction."

 It does not have to be mentioned, because it's implied by how the #DB 
exception is propagated: regardless of its origin it never checks the DPL.  
And user-mode software may well use POPF at any time to set the TF bit in 
the flags register to the same effect, so the OS needs to be prepared for 
a #DB exception it hasn't scheduled itself anyway.

  Maciej