From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5EB5B43849F for ; Wed, 22 Jul 2026 11:37:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784720263; cv=none; b=VZ1wOtENoyg556zLfV3cb1iqUfo6ihTEBsslnBR8RxvecE5S0AwTQOvKlYLz4oww/YY/O5kWcD2scD4FNoAcmpCd+71wXeJyHVw9r7KZXQQtxYdk/3JynqoTqDYXyMz0h1w3ytzqZs8HhTt0FRinzU3zOH9I/Hq7fkG6lvU2kBk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784720263; c=relaxed/simple; bh=fW7lrmD+q58SE5jmSO97rxr4Xexsu6S52JD2mEizFfw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GfoHZ/A4W5N29osMbAiUii+rY43eq4CNX5Prj0UYzHwcLK6rYg16wfB74qpnFA/i+EGlksiyjsfHwi+z54O97JZK+wnONr8olwsxYJ/jE+7kFV98Ha758Fy9tOs7rd95ZVPArv3dcNb+GXBhYuvf3lGaERyiWwWStEcj2a7mRJw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=YT0/Jh5P; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="YT0/Jh5P" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6A60E1595; Wed, 22 Jul 2026 04:37:36 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A28A23F66F; Wed, 22 Jul 2026 04:37:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784720260; bh=fW7lrmD+q58SE5jmSO97rxr4Xexsu6S52JD2mEizFfw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YT0/Jh5POL4D8ATaEQOkmJSkSSQ1D9q64sgAYSBISJ6U4RyQwkApWYwMQ27Qq/V+7 cKp6WHZsUNhTwtsgY+CcHXpHUQ4InrDBZO8hv66tKG3kHC7mf2y1U89DBlcyhlnT27 oS8D8gsVbKDw3sebegNfDHK81gZUAISlowqVQPpo= Date: Wed, 22 Jul 2026 12:37:19 +0100 From: Mark Rutland To: Gavin Shan Cc: Linu Cherian , Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 3/6] arm64: cpufeature: Extend bbml2_noabort support list Message-ID: References: <20260715053408.1950475-1-linu.cherian@arm.com> <20260715053408.1950475-4-linu.cherian@arm.com> <671d0b1e-65f1-461a-aec8-a031c40245bc@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <671d0b1e-65f1-461a-aec8-a031c40245bc@redhat.com> On Thu, Jul 16, 2026 at 10:00:40AM +1000, Gavin Shan wrote: > On 7/15/26 3:34 PM, Linu Cherian wrote: > > C1-Ultra and C1-Premium both suffer from erratum 3683289, > > where Break-Before-Make must be followed to avoid a livelock. > > For both CPUs, the erratum is fixed from r1p1. > > Hence we do not enable BBML2_NOABORT for CPU revisions <= r1p0. > > @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void) > > MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1), > > MIDR_ALL_VERSIONS(MIDR_AMPERE1A), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), > > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), > > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), > > + MIDR_ALL_VERSIONS(MIDR_C1_NANO), > > + MIDR_ALL_VERSIONS(MIDR_C1_PRO), > > + /* Erratum 3683289 fixed in r1p1 */ > > + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), > > + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), > > The revisions for C1_ULTRA and C1_PREMIUM have been limited to > r1p1 to r1p15. How about r2p0 and the revisions after that? We > probably won't get a chance to hit the ceiling? :-) Yes, those should be: MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf), MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf), In general, MIDR_REV_RANGE() doesn't make much sense and should be removed. I have a patch for that hidden in some other MIDR cleanup, so I'll go revive that shortly... Mark.