From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09183435504 for ; Thu, 23 Jul 2026 10:31:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.71 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784802668; cv=none; b=T+695GBmpTv+5+QUuSr/al2kjxFsKZInaFHW2YryY7q+h/TKazvoPE27/t083FytsIJ6qWdBneBN6yCtd3Z1I9p6z2ajhnbyGHvXt8y/O32aK2DhtwrtxpaZYsK2bhy99eJFdQTcZwxeB/FlHZRHItaN1Wwudc1bjIIIgEKQ+VI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784802668; c=relaxed/simple; bh=Xej/JKJCX9/FN4i3ieZAXht1hc34L67qfOs0U+vcbP0=; h=Date:In-Reply-To:Mime-Version:References:Message-ID:Subject:From: To:Cc:Content-Type; b=omKnqHrnKiuAXHP89gL6iERtUVbQV5sBXi+/lxhnF8ZW/YeIOuIj4FEwKRzBM8CW5Ap/jY20ypPAqflV8uQRjzFKi1zimFy8HS2UOWQPltKXAQS6kKg10kKf62OIh+miyIuNZQqTm+fVaFEZjWo1Udh5iFpxGUBaHJbV/QJ5g/4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--aliceryhl.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=BYTeMnoS; arc=none smtp.client-ip=209.85.128.71 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--aliceryhl.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="BYTeMnoS" Received: by mail-wm1-f71.google.com with SMTP id 5b1f17b1804b1-49544a639e9so2371615e9.1 for ; Thu, 23 Jul 2026 03:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1784802663; x=1785407463; darn=vger.kernel.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=Mqgqzxkhdx1tnyQjzJPVNW/eINwechdkO4hcnTDq4+o=; b=BYTeMnoSlESRBoFNJyiu5NYZDlXMdy2q/SNxI/YBxlJwse1WRjHS8NipIv0T4FN63I NYWV7wFzO0hX6sBrI58cZXrueBZksGcqK5PJruxZxWe9RHMJiJwPB+lMACh4Zqh3mz2p S4fqCf2DWm+tHiBzRqxdZs8TQAl1NA5jYCjDYUS8z4jLD+KjlzMaessCH1O9X/UqB/Ds yBX7Z18WLkDM8J/YGoXudG/H5qrNIeCKCT1uihX/FkMq6kZULR48EDi0uXKnhJVLYwmd KXwiXZoiMtHWKkIQ7NlVVDOlO9jKXOe8J3UGOBcmr1neal9jiZqbEy+ZWWhXIenT3MeN NxRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784802663; x=1785407463; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Mqgqzxkhdx1tnyQjzJPVNW/eINwechdkO4hcnTDq4+o=; b=moLB2qV74elpWiMHkVva8HTKIBIf4bowZpwcJFe5SLUX8h7MbR9+jJYjTdhBxFu8cO 4bz5IKWlbeaRr+yIz6rIMAnheOgf9gfjXoNUmQLD+CSdLb+/nidpSLo+TR4Be5JtLbJk RKPyeyA9yqDxgJnVEU7swyR7lUyBO5NVQoDnsDTqv5WU2AbNiq+edcuPTh5lgAGWCtyQ JwLTwTjuQ9Dq/FfJZmlkwkeR06Wx1Vegu4o0SpQDHxkUO0mrewJPZdUXaOq/APHhUunP Vex4GebtFACoG7LlFgvfGbHj5ewPC3YmtrUo41nZ8agBVCUi3iYHdU6wJtAh+mIP/AK2 kSUg== X-Forwarded-Encrypted: i=1; AHgh+RrwbqKagOtlN8Wh/MTESxAtdYj4pyli0pZVq6okA5wkHq5ShE9bzfdwWKwjP6Fc3/IO+TqvqbvmbXhokoA=@vger.kernel.org X-Gm-Message-State: AOJu0YxG2MdkQ0dD4aZgBzis0pzkIN4O3/42uXBfPeHDbYEU+V3fjulx QchePg7vEPFAB5EzRmlpB4/RoFrDc4j4cafQU/mXT6Ny1ejA1IpVUGzOcr9m/4GecKctbAvXeG0 yt3RE5RcUTGnyzuEaUw== X-Received: from wmbjj16.prod.google.com ([2002:a05:600c:6a10:b0:495:5422:15f2]) (user=aliceryhl job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:4e89:b0:495:63e4:7f78 with SMTP id 5b1f17b1804b1-49573ccd115mr30916405e9.10.1784802662821; Thu, 23 Jul 2026 03:31:02 -0700 (PDT) Date: Thu, 23 Jul 2026 10:31:01 +0000 In-Reply-To: <20260723-chid-v2-2-c35e5e9fb3d9@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260723-chid-v2-0-c35e5e9fb3d9@nvidia.com> <20260723-chid-v2-2-c35e5e9fb3d9@nvidia.com> Message-ID: Subject: Re: [PATCH v2 2/4] rust: bitmap: add contiguous area operations From: Alice Ryhl To: Eliot Courtney Cc: Burak Emir , Yury Norov , Miguel Ojeda , Boqun Feng , Gary Guo , "=?utf-8?B?QmrDtnJu?= Roy Baron" , Benno Lossin , Andreas Hindborg , Trevor Gross , Danilo Krummrich , Daniel Almeida , Tamir Duberstein , Alexandre Courbot , "Onur =?utf-8?B?w5Z6a2Fu?=" , David Airlie , Simona Vetter , Greg Kroah-Hartman , John Hubbard , Alistair Popple , Timur Tabi , Zhi Wang , rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, nova-gpu@lists.linux.dev, dri-devel@lists.freedesktop.org Content-Type: text/plain; charset="utf-8" On Thu, Jul 23, 2026 at 05:59:11PM +0900, Eliot Courtney wrote: > Add bindings for area operations on bitmaps. Each one is > made safe by adding some extra checks compared to the underlying C code > (for example, checking bounds) and with additional checks to catch > likely erroneous usage if `CONFIG_RUST_BITMAP_HARDENED` is on. > > The C code uses signed integers for some parameters, for example the > length for `__bitmap_set`, so bounds check against i32::MAX. We can't > rely on `BitmapVec::MAX_LEN` because `Bitmap` may not necessarily be > backed by `BitmapVec`. There's also a few cases where an `align_mask` > can cause an infinite loop in the C code: masks that are not a power > of two minus one, and masks where `self.len() + align_mask` overflows > the alignment step, so check for those. > > Add tests demonstrating the edge cases. > > Signed-off-by: Eliot Courtney > --- > rust/kernel/bitmap.rs | 217 ++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 217 insertions(+) > > diff --git a/rust/kernel/bitmap.rs b/rust/kernel/bitmap.rs > index a43bfe0ec3dc..1395bbe99cbb 100644 > --- a/rust/kernel/bitmap.rs > +++ b/rust/kernel/bitmap.rs > @@ -497,6 +497,127 @@ pub fn next_zero_bit(&self, start: usize) -> Option { > Some(index) > } > } > + > + /// Finds a contiguous area of `nbits` zero bits at or after `start`, aligned per `align_mask`. > + /// > + /// Returns the bit index of the start of the area, or [`None`] if no such area fitting in > + /// the bitmap exists or the `align_mask` is invalid. > + /// > + /// `align_mask` should be `0` (no alignment) or one less than a power of two, in which case the > + /// returned index is a multiple of that power of two. Masks such that `self.len() + align_mask` > + /// overflows are checked and considered invalid, as they can hang the underlying C code. > + /// > + /// # Panics > + /// > + /// Panics if CONFIG_RUST_BITMAP_HARDENED is enabled and `start` is out of bounds or > + /// `align_mask` is invalid. > + /// > + /// # Examples > + /// > + /// ``` > + /// use kernel::alloc::{AllocError, flags::GFP_KERNEL}; > + /// use kernel::bitmap::BitmapVec; > + /// > + /// let mut b = BitmapVec::new(64, GFP_KERNEL)?; > + /// > + /// assert_eq!(Some(0), b.next_zero_area(0, 8, 0)); > + /// b.set(0, 5); > + /// assert_eq!(Some(5), b.next_zero_area(0, 8, 0)); > + /// assert_eq!(Some(8), b.next_zero_area(0, 8, 7)); > + /// assert_eq!(None, b.next_zero_area(0, 65, 0)); > + /// # Ok::<(), AllocError>(()) > + /// ``` > + #[inline] > + pub fn next_zero_area(&self, start: usize, nbits: usize, align_mask: usize) -> Option { Instead of using a `usize` argument, it'd be ideal to use the Alignment type defined in rust/kernel/ptr.rs, since it is guaranteed that the contained value is a power of two, so you can omit all those checks. (Since you need a mask, you'll need to subtract one from the provided Alignment, but that should be fine.) Alice