From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EEF2439F8A for ; Thu, 23 Jul 2026 11:55:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784807747; cv=none; b=n/1ER+v6HLBgWuobsuVXqtbtrhka24MyDamfperihuHzaJIKimcL2xfb3OeVoKJqoC56lVe829fg0iSTzNmBb3PI6VXS12hhuWGDhbSriyLIY3x0AnE6Uezdrli59HyVXD0RKofLY3chFmm4GJx4iCvou3tPTtPrsQOsjMuQGjU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784807747; c=relaxed/simple; bh=VqUTFSQWYZpH8HJgrbZlT45m2AFLEFJS3umcEuZczMQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=hhgTNJ/XkqH3HDKxicCnC6qwIYhFGQluPa1QM8c4uvbaO2x1urMS+MKckIjhaz0Yu0mfvfQpA+H4rQ1ZNPi9QbQIfGd1a1+T2wl/v6aT40zW9cTNc8zWOLUJ02eUzXhE0SGpEANHNs9sThDBJEZkZCg9hYCCVbJHvTs7gxR/m3E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nj77jfU4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nj77jfU4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 967711F000E9; Thu, 23 Jul 2026 11:55:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784807744; bh=kFgZ2eBiNcwcGV3DI3hnI/6tbw1e4YfJ27gXmH8uagg=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=nj77jfU4D9f3cOSMpe6/E22EDjVDPGVZESw2lM59O6h7JrJOa8A9D+zAy+6rw+946 xOQKGtfaVaKtBT4mqvftSCHjWUENaoSsZopVtzQvrBig5e2xlfRocdkU9fvZRhkcY3 IeI/sq0liOOJ2bZCs/MVroaciCJ4fRB7fOuZTPNWm5M+WzMv/VXm5YotBiVXfRq/K1 dzIAgYP5p2IQ6jP4OeSdvvF7Pm3SxtVHxe+U3B0jxgDvnusICIYkaXzKRCyyCEvaim TrIxzM7z+6yyZcreXtNXMEGXAxyXuKSIUZD3VgUj9eq9g+ekjqr+MAX+qsVNMPLnrJ 0w2RTBp0dGnhA== Date: Thu, 23 Jul 2026 17:22:00 +0530 From: Naveen N Rao To: Ingo Molnar Cc: Borislav Petkov , Dave Hansen , linux-kernel@vger.kernel.org, x86@kernel.org, Thomas Gleixner , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" Subject: Re: [PATCH v4 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Message-ID: References: <2d18caf834a2e66e4c6787e3c3058fd6bb6e5d3e.1784785046.git.naveen@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Ingo, On Thu, Jul 23, 2026 at 10:02:51AM +0200, Ingo Molnar wrote: > > * Naveen N Rao (AMD) wrote: > > > For AMD family 0x10, EILVT offsets are not assigned by BIOS and is > > instead assigned by picking the next available EILVT offset. Use the > > maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than > > an arbitrary maximum EILVT count when looking for the next available > > EILVT offset. > > > > Signed-off-by: Naveen N Rao (AMD) > > Tested-by: Manali Shukla > > --- > > arch/x86/events/amd/ibs.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c > > index 3531f9c23b8c..555912ac520f 100644 > > --- a/arch/x86/events/amd/ibs.c > > +++ b/arch/x86/events/amd/ibs.c > > @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) > > > > preempt_disable(); > > /* find the next free available EILVT entry, skip offset 0 */ > > - for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { > > + for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { > > Nit: > > s/APIC_EILVT_NR_AMD_10H > /APIC_EILVT_NR_MAX_AMD_10H > > to make it clear at first sight that this is a (family specific) > maximum, not some default count or other random value. Makes sense - I will send that as a separate cleanup on top of this series. Thanks for the review! - Naveen