From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 167032D7DEA for ; Thu, 23 Jul 2026 14:46:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784818004; cv=none; b=RBQ0QIuyenEHsE3Ak8cEm2zQ3mtP9c6ruS56yt7y+HvJ22nOitAgm57QJOgjTyFpvUB5xUoutzSrzUJwKW2Wv3RCpL81YR3QDCJJkoR9miJ5jhJc0Y7haHwZWyr4b5aBFTfCk4BEwo2RhGlqudnz+R7Z6hojlUBfYW7/+Zh5h9o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784818004; c=relaxed/simple; bh=U+b+te5CuUryG2Fgq9GizoEuCCqRmCv58/tvMkBP6Gs=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=GSbLHz7t7FdTGxl90jYNXwOpwIbfNPzj2yVzbrlpjKYC6gS22OQr7nArz2ymne8XIIQvs1tEd6B622ArO4DZ37NY0ftLbk6AScJUfoZyPqfbDwFXR4nKbvs2eGHwzaxSi4Bi73BqNzQBPgYSN22ldc2YonvMK7IB3DFyc7lEXp8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id C0D1E1F000E9; Thu, 23 Jul 2026 14:46:40 +0000 (UTC) Date: Thu, 23 Jul 2026 08:46:21 -0600 From: Keith Busch To: Fengnan Chang Cc: linux-nvme@lists.infradead.org, Jens Axboe , Christoph Hellwig , Sagi Grimberg , Bart Van Assche , Andy Shevchenko , Thomas Gleixner , Jun Zeng , Gang Cao , Jun I Jin , Liang A Fang , Yong Hu , linux-kernel@vger.kernel.org, Guzebing Subject: Re: [RFC PATCH] nvme-pci: adaptively poll completions on busy queues Message-ID: References: <20260723120556.58670-1-changfengnan@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260723120556.58670-1-changfengnan@bytedance.com> On Thu, Jul 23, 2026 at 08:05:56PM +0800, Fengnan Chang wrote: > +static void nvme_adaptive_mask_irq(struct nvme_queue *nvmeq, int irq) > +{ > + struct nvme_dev *dev = nvmeq->dev; > + struct pci_dev *pdev = to_pci_dev(dev->dev); > + > + if (pdev->msi_enabled) { > + writel(BIT(nvmeq->cq_vector), dev->bar + NVME_REG_INTMS); > + readl(dev->bar + NVME_REG_INTMS); Why do you have the readl? That's not necesary. > + } else { > + disable_irq_nosync(irq); > + } > +} > + > +static void nvme_adaptive_unmask_irq(struct nvme_queue *nvmeq, int irq) > +{ > + struct nvme_dev *dev = nvmeq->dev; > + struct pci_dev *pdev = to_pci_dev(dev->dev); > + > + clear_bit(NVMEQ_ADAPTIVE_POLLING, &nvmeq->flags); > + if (pdev->msi_enabled) { > + writel(BIT(nvmeq->cq_vector), dev->bar + NVME_REG_INTMC); > + readl(dev->bar + NVME_REG_INTMS); Same here.