From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-ed1-f50.google.com (mail-ed1-f50.google.com [209.85.208.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B025547CA67 for ; Thu, 23 Jul 2026 15:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.50 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784819755; cv=none; b=D5RhQxP/ULbAxpNx1Ii4rjYLFXp6Sr11WD76FrL8cv+lHppSjssvShv5JEqAKJJDp4yMA7gEhdblvrBrmRevhySMj+reR0/Qq3QmCkKSw0sGB6KMUOm0dWY0VtX4D8q9yuLATZ01RjSBNY4ofxbAL8OWktgWu8HRzjdTtEcKVQY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784819755; c=relaxed/simple; bh=AbZpuHYdT9bmv8owVlBDCivQtCLS1/6F0ma+B6QZBZ4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=pe/vc702MG1vPaX/D0+bBp5u3NYH9kJ80wu0YCFNHB52DH8jejyz6KgMlqrNdKEOzhwTPqcEZ/Y4dd9deKCKcmL7FDaNw42WPL9ZAa9zXjborJ1dLW7fUX5OG/wOv/0vSCmPh5CF0NTlI5t59il42hkK91Hv6NKjRyvMVY82tbs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=XCTDYJLE; arc=none smtp.client-ip=209.85.208.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="XCTDYJLE" Received: by mail-ed1-f50.google.com with SMTP id 4fb4d7f45d1cf-69f21b7f6cdso11261a12.0 for ; Thu, 23 Jul 2026 08:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1784819752; x=1785424552; darn=vger.kernel.org; h=in-reply-to:content-disposition:content-type:mime-version :references:message-id:subject:cc:to:from:date:from:to:cc:subject :date:message-id:reply-to:content-type; bh=rHtkaJhyp7hvNXFM/a/du/ejeo788OAfuxw7sqTwA3Q=; b=XCTDYJLE9M88vaf3xB7Hjtew9piycvGDlbYXS8xjwAvvzc60Rc6Qzk4ZLyYFsph6cY eCHdLsVcHh7mQ4MHxnORuGjzdcd+ztWvX1uvAeHpEqaA4Obzo+l9FepcYNEmF3nfvKJU X45H74YvNxNUleA+U2N+gw0j3fxw1fltNk5Vv5GFNqo/VIcQQdMubl9umD8eBL13getY FN62czqShV0N6r2g6jozdqR4L85gBLzoj5B9eEgdfVQaUbFYcRPjF7z+A4J6F6/i7ZD/ UcW9F5A5UNqQ/alJNwa2IwKJSGuzZS1m1VQjtruGTUk39UiR65veVDHAPaDcTuIrvLZO UcPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784819752; x=1785424552; h=in-reply-to:content-disposition:content-type:mime-version :references:message-id:subject:cc:to:from:date:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=rHtkaJhyp7hvNXFM/a/du/ejeo788OAfuxw7sqTwA3Q=; b=Uxany26iVmMxV8wmRSAa0PgjriNWkQyeAwpRjLGoYbRd0mQLybDoe/Xz5CH9HZDmJV LSmn784HJBrnY7q9Ok9yHldmyk4O7ogBl66PMB3Iu5rgolqEZm1d1+/Ovurw/LR618S3 fS8JDibfbVAQc+ghUooW0mWIocRR9hhrtASweFKGOatxa5kl+BfJa8ARxSdbSrZsh1tr 7ainfnwEUPfDjPKNylH2CNDmQ2h5UEAymrbgT1a5gg+hkeQlQqlvpZUge/8y5nBfUy4O vxRnGd4tVeOtOX/Gi92gk2oGqQCw7CmIFHd81DJkUTC42dx4Q3TwJmrrLm8uMyIp+NrW Juuw== X-Forwarded-Encrypted: i=1; AHgh+RpZu6xtiTnAPBND1Gm22+vX7r93tpfUA6W75ePj0slLJm3x0zuy8cLlB5VSbD89fNv3bdysnKqgOV62rsw=@vger.kernel.org X-Gm-Message-State: AOJu0Ywk/CLGU721VuKVayCT2gtFvg8S1DIZdFxAVDv3rc9OYsWoRPqe 92rQTnRz6i1IHqFboK7/06zQou7X0JB/TqP9VtUq1CUHRoe/LLzi5y/x48tGHNRP+w== X-Gm-Gg: AR+sD10jOh6Nqjdr60sbuMAfqY5xmUYIhQYeDf6cP0HGAGaQQuCukhoRM6Nwhy9jJZR 0gsLNprivYXBeo/XZRE6Fuf3gfUlaAjaE6QyMgWSI69FNyFpO+RHJrPE66fI6RqSimGnohJkXXu u/ObYKU37BpL5A5fEIZpJM68LXJ43jAYq7SPK85nJet3d6kpub3VC2iqvMwv1x0XaUs2jHdn8Ga 72n6++VQM0+BSsv2mkZgz3gmLnxdO1g8bvsKfZSl7uORfwBS62S6mDK2SxPcqHvTokwuS/gbHV+ nZh0Ro6f9KXcaZtEEgyr7GlylxB/XjAGl2xlbdrH6IPAd1tffPJNjpPl4zQvlLWcPA6/rLoYYW6 khWYcNC8Q50Q0IosD0ZgtGgldWPfzL5oIuqUS9DVOjOKS82ueav5eb4MqUfbHPQdC4ay6gUBMYj XRptoLBdCtdsl9hkCg2VXShe90lDUFLbhcBJWc/w== X-Received: by 2002:a05:6402:a6c9:20b0:697:5678:bc77 with SMTP id 4fb4d7f45d1cf-69f6cd0cdb9mr48696a12.9.1784819751162; Thu, 23 Jul 2026 08:15:51 -0700 (PDT) Received: from google.com (220.60.76.34.bc.googleusercontent.com. [34.76.60.220]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69f34b9b064sm2548716a12.11.2026.07.23.08.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2026 08:15:48 -0700 (PDT) Date: Thu, 23 Jul 2026 15:15:42 +0000 From: Mostafa Saleh To: Sebastian Ene Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev, catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, keirf@google.com Subject: Re: [PATCH v7 14/24] iommu/arm-smmu-v3-kvm: Shadow the command queue Message-ID: References: <20260715115906.2664882-1-smostafa@google.com> <20260715115906.2664882-15-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Hi Seb, On Thu, Jul 23, 2026 at 02:55:08PM +0000, Sebastian Ene wrote: > On Wed, Jul 15, 2026 at 11:58:55AM +0000, Mostafa Saleh wrote: > > + * size as the host. > > + * Only populate base_dma and llq.max_n_shift, the hypervisor will init > > + * the rest. > > + */ > > + cmdq_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, SMMU_KVM_CMDQ_ORDER); > > + if (!cmdq_base) > > + return -ENOMEM; > > Hi Mostafa, > > Isn't this over-allocating when PAGE_SIZE > 4kB ? Yes, that means the queue have different size depending on PAGE_SIZE, In the kernel driver CMDQ_MAX_SZ_SHIFT is defined in terms of page size also, but I think in the hypervisor it doesn't really matter, I can change this to a fixed size and use alloc_pages_exact(). > > > + > > + smmu->cmdq.base_dma = virt_to_phys(cmdq_base); > > + smmu->cmdq.llq.max_n_shift = SMMU_KVM_CMDQ_ORDER + PAGE_SHIFT - CMDQ_ENT_SZ_SHIFT; > > + > > if (of_dma_is_coherent(dev->of_node)) > > smmu->features |= ARM_SMMU_FEAT_COHERENCY; > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c > > index af06c832fc6f..9f76f4e82341 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c > > @@ -11,7 +11,6 @@ > > #include > > > > #include "arm_smmu_v3.h" > > -#include "../arm-smmu-v3.h" > > > > size_t __ro_after_init kvm_hyp_arm_smmu_v3_count; > > struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus; > > @@ -21,10 +20,68 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus; > > (smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \ > > (smmu)++) > > > > +#define cmdq_size(cmdq) ((1 << ((cmdq)->llq.max_n_shift)) * CMDQ_ENT_DWORDS * 8) > > + > > +static bool is_cmdq_enabled(struct hyp_arm_smmu_v3_device *smmu) > > +{ > > + return FIELD_GET(CR0_CMDQEN, smmu->cr0); > > +} > > + > > +/* > > + * CMDQ, STE host copies are accessed by the hypervisor, we share them to > > + * - Prevent the host from passing protected VM memory. > > + * - Having them mapped in the hyp page table. > > + */ > > +static int smmu_share_pages(phys_addr_t addr, size_t size) > > +{ > > + size_t nr_pages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT; > > + phys_addr_t base = addr & PAGE_MASK; > > + int i, ret; > > + > > + for (i = 0 ; i < nr_pages ; ++i) { > > + if (__pkvm_host_share_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT)) { > > + while (i--) > > + __pkvm_host_unshare_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT); > > + return -EPERM; > > + } > > + } > > + > > + ret = hyp_pin_shared_mem(hyp_phys_to_virt(base), > > + hyp_phys_to_virt(base + nr_pages * PAGE_SIZE)); > > + if (ret) { > > + for (i = 0 ; i < nr_pages ; ++i) > > + __pkvm_host_unshare_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT); > > + } > > + > > + return ret; > > +} > > + > > +static int smmu_unshare_pages(phys_addr_t addr, size_t size) > > +{ > > + size_t nr_pages = PAGE_ALIGN(size + (addr & ~PAGE_MASK)) >> PAGE_SHIFT; > > + phys_addr_t base = addr & PAGE_MASK; > > + int i, ret; > > + > > + hyp_unpin_shared_mem(hyp_phys_to_virt(base), > > + hyp_phys_to_virt(base + nr_pages * PAGE_SIZE)); > > + > > + for (i = 0 ; i < nr_pages ; ++i) { > > + ret = __pkvm_host_unshare_hyp((base + i * PAGE_SIZE) >> PAGE_SHIFT); > > + if (ret) > > + return ret; > > + } > > + > > + return 0; > > +} > > + > > /* Put the device in a state that can be probed by the host driver. */ > > static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu) > > { > > WARN_ON(__pkvm_hyp_donate_host_mmio(smmu->mmio_addr, smmu->mmio_size)); > > + > > + if (smmu->cmdq.base) > > + WARN_ON(__pkvm_hyp_donate_host(smmu->cmdq.base_dma >> PAGE_SHIFT, > > + cmdq_size(&smmu->cmdq) >> PAGE_SHIFT)); > > smmu->base = NULL; > > } > > > > @@ -75,6 +132,31 @@ static int smmu_probe(struct hyp_arm_smmu_v3_device *smmu) > > return 0; > > } > > > > +/* > > + * The kernel part of the driver will allocate the shadow cmdq, > > + * and zero it. This function only donates it. > > + */ > > +static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu) > > +{ > > + size_t cmdq_nr_pages = cmdq_size(&smmu->cmdq) >> PAGE_SHIFT; > > + int ret; > > + > > + ret = __pkvm_host_donate_hyp(smmu->cmdq.base_dma >> PAGE_SHIFT, cmdq_nr_pages); > > + if (ret) > > + return ret; > > + > > + smmu->cmdq.base = hyp_phys_to_virt(smmu->cmdq.base_dma); > > + smmu->cmdq.prod_reg = smmu->base + ARM_SMMU_CMDQ_PROD; > > + smmu->cmdq.cons_reg = smmu->base + ARM_SMMU_CMDQ_CONS; > > + smmu->cmdq.q_base = smmu->cmdq.base_dma | > > + FIELD_PREP(Q_BASE_LOG2SIZE, smmu->cmdq.llq.max_n_shift); > > + smmu->cmdq.ent_dwords = CMDQ_ENT_DWORDS; > > + writel_relaxed(0, smmu->cmdq.prod_reg); > > + writel_relaxed(0, smmu->cmdq.cons_reg); > > + writeq_relaxed(smmu->cmdq.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); > > do we need a dsb here ? I do not think so, why would it be needed? No data written at this point. When commands are written, writel() is used to advance the queue pointer which includes a barrier to enusre that the commands are observed. Thanks, Mostafa > > > Thanks, > Sebastian