From: Frank Li <Frank.li@oss.nxp.com>
To: haibo.chen@oss.nxp.com
Cc: Han Xu <han.xu@nxp.com>, Yogesh Gaur <yogeshgaur.83@gmail.com>,
Mark Brown <broonie@kernel.org>,
linux-spi@vger.kernel.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, Haibo Chen <haibo.chen@nxp.com>
Subject: Re: [PATCH v2 2/3] spi: spi-nxp-fspi: enter stop mode before reconfiguring MCR0 and DLL
Date: Tue, 28 Jul 2026 10:16:36 -0500 [thread overview]
Message-ID: <amjH1P7Q6tZkEuoL@SMW015318> (raw)
In-Reply-To: <20260728-fspi-clock-v2-2-dbe786a4a6eb@nxp.com>
On Tue, Jul 28, 2026 at 06:18:09PM +0800, haibo.chen@oss.nxp.com wrote:
> From: Haibo Chen <haibo.chen@nxp.com>
>
> In nxp_fspi_select_mem() the RX sample clock source (MCR0[RXCLKSRC])
> and the DLL control registers (DLLxCR) are reconfigured while the
> FlexSPI module is still enabled. According to the FlexSPI reference
> manual initialization sequence, MCR0 and the DLL control registers
> should be programmed while the module is in stop mode, i.e. with
> MCR0[MDIS] set to 1, and the module re-enabled (MCR0[MDIS] = 0)
> afterwards.
>
> Wrap the RX sample clock source selection and the DLL calibration/
> override reconfiguration in a stop-mode window to align with the RM
> and avoid reconfiguring timing-critical registers while the module is
> active.
>
> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> drivers/spi/spi-nxp-fspi.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
> index 6de6d432cdcb2ee383a02d72f20000045903e176..a426b8d92193a4e303f411cd17c16cb31c3f3873 100644
> --- a/drivers/spi/spi-nxp-fspi.c
> +++ b/drivers/spi/spi-nxp-fspi.c
> @@ -867,6 +867,7 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
> unsigned long rate = op->max_freq;
> int ret;
> uint64_t size_kb;
> + u32 reg;
>
> /*
> * Return when following condition all meet,
> @@ -896,6 +897,15 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
>
> dev_dbg(f->dev, "Target device [CS:%x] selected\n", spi_get_chipselect(spi, 0));
>
> + /*
> + * Per the FlexSPI reference manual (initialization sequence), MCR0 and
> + * the DLL control registers should be configured while the module is in
> + * stop mode (MCR0[MDIS] = 1). Enter stop mode before reconfiguring the
> + * RX sample clock source and the DLL, then exit stop mode afterwards.
> + */
> + reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> + fspi_writel(f, reg | FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
> +
> nxp_fspi_select_rx_sample_clk_source(f, op_is_dtr);
> rate = min(f->max_rate, op->max_freq);
>
> @@ -928,6 +938,10 @@ static void nxp_fspi_select_mem(struct nxp_fspi *f, struct spi_device *spi,
> else
> nxp_fspi_dll_override(f);
>
> + /* Exit stop mode now that MCR0 and the DLL have been reconfigured. */
> + reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> + fspi_writel(f, reg & ~FSPI_MCR0_MDIS, f->iobase + FSPI_MCR0);
> +
> f->pre_op_rate = op->max_freq;
>
> f->selected = spi_get_chipselect(spi, 0);
>
> --
> 2.34.1
>
>
next prev parent reply other threads:[~2026-07-28 15:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-28 10:18 [PATCH v2 0/3] Few fix/improvement for spi-nxp-fspi haibo.chen
2026-07-28 10:18 ` [PATCH v2 1/3] spi: spi-nxp-fspi: add per-SoC SDR/DTR clock rate limits for all supported SoCs haibo.chen
2026-07-28 15:14 ` Frank Li
2026-07-28 10:18 ` [PATCH v2 2/3] spi: spi-nxp-fspi: enter stop mode before reconfiguring MCR0 and DLL haibo.chen
2026-07-28 15:16 ` Frank Li [this message]
2026-09-24 10:07 ` Michael Walle
2026-09-24 10:25 ` Bough Chen (OSS)
2026-09-28 10:42 ` Bough Chen (OSS)
2026-07-28 10:18 ` [PATCH v2 3/3] spi: spi-nxp-fspi: propagate clock reconfig failures in nxp_fspi_select_mem() haibo.chen
2026-07-30 12:14 ` [PATCH v2 0/3] Few fix/improvement for spi-nxp-fspi Mark Brown
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