From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 224F32DEA8C for ; Tue, 28 Jul 2026 16:04:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785254643; cv=none; b=KXvCAmSGgqz9YSLE17lckEJVcyNB9zzd/I1znH6TnTqsAONcCwP+vWvTdnIIv4UuMy9hQAmcFM0ZBXR/zgBeMCyC7Rav8IJIIjDf40uaq9DlC3OcqY/LmIiZN/rLB8h00/L0vFLKl0GjQVkxNpAc6eGlzZGweKTyu+cVZNCWxbk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785254643; c=relaxed/simple; bh=e9+N00NeQ9x1r37z54aVe+DJvWWs2shWjzXfn8Am9vQ=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LHo0Vl6vi4BSCf9YGtR1FYmRYGq0Gz8+JPVBurzziD6ST89iEXcadi9pvfyZAUtvpdj25HdeCxPE3sabdPj+7aftZeNDLh68eBi7W8aStSKFr69Jfejv59w26fgKXKf/7TT1XmHrFw4j/e6hgSugH7roKiat/M9omLhFzSdzVLg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=C5YBB4yE; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="C5YBB4yE" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F493169E; Tue, 28 Jul 2026 09:03:57 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A33B23F763; Tue, 28 Jul 2026 09:03:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785254641; bh=e9+N00NeQ9x1r37z54aVe+DJvWWs2shWjzXfn8Am9vQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=C5YBB4yEzvF3RdmWrG9x1xwKeAziCFV76kZXwnumQPvwJ39HcBFcmKSjThfUAgH5i 43m2HRqQyWkZH6W085Em5SKbA3b2cNQ54HUp/R35Q8NdBxbf0J0xTtpjj444PS3Cf3 UjGzL95+YySTLMEtpGNEeU5nTUI3iG8b9e0BGatg= Date: Tue, 28 Jul 2026 17:03:57 +0100 From: Mark Rutland To: Peter Zijlstra Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, maz@kernel.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: Re: [RFC PATCH 06/13] arm64: percpu: Add infrastructure for preemptible this_cpu_*() ops Message-ID: References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-7-mark.rutland@arm.com> <20260728141958.GV751831@noisy.programming.kicks-ass.net> <20260728143016.GB921102@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260728143016.GB921102@noisy.programming.kicks-ass.net> On Tue, Jul 28, 2026 at 04:30:16PM +0200, Peter Zijlstra wrote: > On Tue, Jul 28, 2026 at 04:19:58PM +0200, Peter Zijlstra wrote: > > On Tue, Jul 28, 2026 at 01:38:52PM +0100, Mark Rutland wrote: > > > > > With the scheme added in this patch, this can be compiled as: > > > > > > | : > > > | mrs x2, sp_el0 > > > | mov x4, #0xc80 > > > | strh w4, [x2, #20] > > > | mrs x4, tpidr_el1 > > > | add x3, x0, x4 > > > > Which it then recomputes, and so is harmless. > > Here! > > > > | 1: ldxr x6, [x3] > > > | add x6, x6, x1 > > > | stxr w5, x6, [x3] > > > | cbnz w5, 1b > > > > If we get here and interrupts happens, we recompute pointlessly, no harm > > done. > > > > Anyway, per this sequence there is no point in ever doing the fixup. So > > perhaps give a better example? > > Nevermind, brain just wasn't working right, when interrupt happens at > 'Here!' above, it needs the fixup, irrespective of the atomic type. Yep! Note that the atomic type doesn't change things. We need the fixup even if preemption happens *within* the LDXR...STXR loop, since the inline sequences branches back to the LDXR, *without* recalculating the addr or offset, and the fixup *does not* alter the PC. It's a bit awkaward to spell that out in the commit message without unrolling the loop :/ Mark.