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Tue, 28 Jul 2026 15:15:10 -0700 (PDT) Received: from localhost ([2001:19f0:8000:3e6e:5400:6ff:fe38:3d01]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d022a18abasm2246025ad.5.2026.07.28.15.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Jul 2026 15:15:09 -0700 (PDT) Date: Wed, 29 Jul 2026 06:14:59 +0800 From: Inochi Amaoto To: Junhui Liu , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Inochi Amaoto , Samuel Holland , Anup Patel , Guodong Xu Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Conor Dooley , Inochi Amaoto Subject: Re: [PATCH RFC 5/7] irqchip/aclint-sswi: Add generic riscv,aclint-sswi match Message-ID: References: <20260729-k3-aclint-v1-0-aef88614d3a5@pigmoral.tech> <20260729-k3-aclint-v1-5-aef88614d3a5@pigmoral.tech> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260729-k3-aclint-v1-5-aef88614d3a5@pigmoral.tech> On Wed, Jul 29, 2026 at 12:36:31AM +0800, Junhui Liu wrote: > Add match entry for the generic "riscv,aclint-sswi" compatible string. > This allows future SoCs with standard ACLINT SSWI implementations to > directly reuse the driver via the generic fallback compatible (at least > until hardware-specific quirks are identified). > > Signed-off-by: Junhui Liu > --- > drivers/irqchip/irq-aclint-sswi.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/irqchip/irq-aclint-sswi.c b/drivers/irqchip/irq-aclint-sswi.c > index ca06efd86fa1..2bd40c3ea288 100644 > --- a/drivers/irqchip/irq-aclint-sswi.c > +++ b/drivers/irqchip/irq-aclint-sswi.c > @@ -179,6 +179,7 @@ static int __init generic_aclint_sswi_early_probe(struct device_node *node, > } > IRQCHIP_DECLARE(mips_p8700_sswi, "mips,p8700-aclint-sswi", generic_aclint_sswi_early_probe); > IRQCHIP_DECLARE(nuclei_ux900_sswi, "nuclei,ux900-aclint-sswi", generic_aclint_sswi_early_probe); > +IRQCHIP_DECLARE(riscv_sswi, "riscv,aclint-sswi", generic_aclint_sswi_early_probe); > Again, use vendor specific name for irqchip declaration. > /* THEAD variant */ > #define THEAD_C9XX_CSR_SXSTATUS 0x5c0 > > -- > 2.55.0 > Reagrds, Inochi