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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d022bf8880sm8677205ad.66.2026.07.29.02.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jul 2026 02:50:55 -0700 (PDT) Date: Wed, 29 Jul 2026 02:50:53 -0700 From: Qiang Yu To: Konrad Dybcio Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Manivannan Sadhasivam , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 4/6] arm64: dts: qcom: glymur-crd: Add PHY supplies for pcie3_phy Message-ID: References: <20260724-glymur_linkmode_0724-v7-0-65c8469c6b65@oss.qualcomm.com> <20260724-glymur_linkmode_0724-v7-4-65c8469c6b65@oss.qualcomm.com> <74907d0a-cf14-43b6-bcfb-8c283926a820@oss.qualcomm.com> <2091d5bf-8c76-479b-98fd-fc75b3adf644@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Info: AW1haW4tMjYwNzI5MDA4MCBTYWx0ZWRfX1rhkgcA4JBGK U7RoAb4mhypMW/4lLc7Qqch05s8LFh++JX3C48LZeI9q4YoUNnt6DTx6utHT/nSd8Mzm3HaRxlw baaerm8dNiTG/5b9npEjfH2YFfwNCVQ= X-Proofpoint-ORIG-GUID: 3MCBL4vblvOSNXKqj47BRhZsGqgfkDdK X-Proofpoint-GUID: 3MCBL4vblvOSNXKqj47BRhZsGqgfkDdK X-Authority-Analysis: v=2.4 cv=AaaB2XXG c=1 sm=1 tr=0 ts=6a69cd01 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=6I5spZTCEmWeGOySesgA:9 a=CjuIK1q_8ugA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzI5MDA4MCBTYWx0ZWRfX/QW2q68pNFQa hx8gLGLrNY2wnS12xdYrYwWK6JIMnQMChb2Pl30n7Qx70va9fHafC6siYHx1fjdtY1ceOOps/Qg /wxn4SnXunPV6Bx9id8IeVBk52iaTvrqFByB00ENrGTOUXzCEq4/Y/uCwHJ59J/VLM+r2ScGY+x IvwxieMxXXlSa3UXRLiWXIHOgylu/V/iJhgNxMkAq20kfArkTg3k84AOXg8o8aRfoAskFVcGIXo oUg5ffx0OuZOiau0yIhmUB5Fk2YdTVNmWsHLXJdgx5Jtg/Qv9MM8l8177THnXwjqEmHZzs4gsz/ d77Gu0mhtVcGmDXh7H/fjk9sDOaiLyPULlKDeazEWZ3H2kIX/jvofYHQmy+rxsEfuZPcgtvDV2g noDFe6vwbERiqplKXmgen1oNNmi01V2qhrGHr9Xm1gEoo4G8Wa+T0JnINz60aL9oFw/+D5PLcjN i285SrDTbkhHDmQUtcg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-29_03,2026-07-28_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607290080 On Wed, Jul 29, 2026 at 11:22:45AM +0200, Konrad Dybcio wrote: > On 7/29/26 11:11 AM, Qiang Yu wrote: > > On Wed, Jul 29, 2026 at 10:30:27AM +0200, Konrad Dybcio wrote: > >> On 7/29/26 8:45 AM, Qiang Yu wrote: > >>> On Mon, Jul 27, 2026 at 04:47:15PM +0200, Konrad Dybcio wrote: > >>>> On 7/24/26 12:01 PM, Qiang Yu wrote: > >>>>> CRD wires the shared Gen5x8 PCIe PHY's regulator supplies through > >>>>> board-specific PMIC rails. Add the vdda-phy, vdda-pll, and > >>>>> vdda-refgen0p9/1p2 supplies for &pcie3_phy. > >>>>> > >>>>> Signed-off-by: Qiang Yu > >>>>> --- > >>>>> arch/arm64/boot/dts/qcom/glymur-crd.dts | 8 ++++++++ > >>>>> 1 file changed, 8 insertions(+) > >>>>> > >>>>> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts > >>>>> index 6125617de82a..0aae613a33ad 100644 > >>>>> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts > >>>>> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts > >>>>> @@ -28,3 +28,11 @@ &mdss_dp1 { > >>>>> &mdss_dp1_out { > >>>>> link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>; > >>>>> }; > >>>>> + > >>>>> +&pcie3_phy { > >>>>> + vdda-phy-supply = <&vreg_l3c_e1_0p89>; > >>>>> + vdda-pll-supply = <&vreg_l2c_e1_1p14>; > >>>>> + > >>>>> + vdda-refgen0p9-supply = <&vreg_l1c_e1_0p82>; > >>>>> + vdda-refgen1p2-supply = <&vreg_l4f_e1_1p08>; > >>>> > >>>> I'm guessing you also meant to enable it here > >>> > >>> No, we need to keep it as disabled because pcie3b is not enabled by > >>> default on glymur crd. > >>> > >>> See the fake pcie3b_phy be dropped, it is disabled > >>> https://lore.kernel.org/all/20260420133616.88740-2-krzysztof.kozlowski@oss.qualcomm.com/ > >> > >> I think there are SKUs with dual-NVMe that use it > > > > But the pcie3b controller node is also disabled, should I enable it in > > this series? > > Do we know what happens if UEFI sets this to x8-mode? (is that even UEFI will not set it two x8 mode on crd. > a concern on CRDs specifically though?) Will the second controller fail > to probe and become a sync_state hog? PCIe3b is not enabled in UEFI by default, if we enable it here, we will see probe fail. - Qiang Yu